{"id":"https://openalex.org/W4410810364","doi":"https://doi.org/10.1109/fccm62733.2025.00050","title":"RapidPnR: Accelerating the Physical Design for FPGAs via Design-Level Parallelism","display_name":"RapidPnR: Accelerating the Physical Design for FPGAs via Design-Level Parallelism","publication_year":2025,"publication_date":"2025-05-04","ids":{"openalex":"https://openalex.org/W4410810364","doi":"https://doi.org/10.1109/fccm62733.2025.00050"},"language":"en","primary_location":{"id":"doi:10.1109/fccm62733.2025.00050","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fccm62733.2025.00050","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE 33rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Wanzheng Weng","orcid":null},"institutions":[{"id":"https://openalex.org/I30809798","display_name":"ShanghaiTech University","ror":"https://ror.org/030bhh786","country_code":"CN","type":"education","lineage":["https://openalex.org/I30809798"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Wanzheng Weng","raw_affiliation_strings":["School of Information Science and Technology, ShanghaiTech University,Shanghai,China"],"affiliations":[{"raw_affiliation_string":"School of Information Science and Technology, ShanghaiTech University,Shanghai,China","institution_ids":["https://openalex.org/I30809798"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081772659","display_name":"Pingqiang Zhou","orcid":"https://orcid.org/0000-0001-9515-9302"},"institutions":[{"id":"https://openalex.org/I30809798","display_name":"ShanghaiTech University","ror":"https://ror.org/030bhh786","country_code":"CN","type":"education","lineage":["https://openalex.org/I30809798"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Pingqiang Zhou","raw_affiliation_strings":["School of Information Science and Technology, ShanghaiTech University,Shanghai,China"],"affiliations":[{"raw_affiliation_string":"School of Information Science and Technology, ShanghaiTech University,Shanghai,China","institution_ids":["https://openalex.org/I30809798"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I30809798"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.09448323,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"278","last_page":"278"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.7408518195152283},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.704025387763977},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6375274658203125},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5649722814559937},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.5453599691390991},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5075656175613403},{"id":"https://openalex.org/keywords/task-parallelism","display_name":"Task parallelism","score":0.428554505109787},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.284824401140213},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.1555754542350769}],"concepts":[{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.7408518195152283},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.704025387763977},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6375274658203125},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5649722814559937},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.5453599691390991},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5075656175613403},{"id":"https://openalex.org/C42992933","wikidata":"https://www.wikidata.org/wiki/Q691169","display_name":"Task parallelism","level":3,"score":0.428554505109787},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.284824401140213},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.1555754542350769}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fccm62733.2025.00050","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fccm62733.2025.00050","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE 33rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4300000071525574,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W3161630314","https://openalex.org/W4211022608","https://openalex.org/W4293023445","https://openalex.org/W4403278520"],"related_works":["https://openalex.org/W2950520577","https://openalex.org/W1501159154","https://openalex.org/W74409296","https://openalex.org/W2003935582","https://openalex.org/W2567390125","https://openalex.org/W4405088460","https://openalex.org/W1554644772","https://openalex.org/W305742777","https://openalex.org/W2940653809","https://openalex.org/W2468095077"],"abstract_inverted_index":{"The":[0,30],"runtime":[1,116],"of":[2,18,27,33,40,48,72,93,108],"physical":[3,34,65,91,131],"design":[4,35,41,66,92,126,132],"has":[5],"become":[6],"a":[7,60,106],"critical":[8],"issue":[9],"for":[10],"FPGA":[11,28],"development":[12],"as":[13],"the":[14,23,38,46,70,82,101,115,124,130,136],"scale":[15],"and":[16,50,63,96,121],"complexity":[17],"circuit":[19,110],"designs":[20],"surge":[21],"with":[22],"increasing":[24],"logic":[25],"capacity":[26],"devices.":[29],"time-consuming":[31],"process":[32],"significantly":[36],"extends":[37],"cycle":[39],"iteration,":[42],"which":[43],"heavily":[44],"impacts":[45],"efficiency":[47],"debugging":[49],"architecture":[51],"optimization.":[52],"To":[53],"address":[54],"this":[55,57],"issue,":[56],"work":[58],"proposes":[59],"generic,":[61],"fully-automated":[62],"split-and-parallel":[64],"flow":[67,79,113,133],"to":[68,129],"accelerate":[69],"deployment":[71],"large-scale":[73],"circuits":[74],"on":[75,105],"FPGAs.":[76],"Specifically,":[77],"our":[78,112],"automatically":[80],"partitions":[81],"synthesized":[83],"netlist":[84],"into":[85,100],"multiple":[86],"smaller":[87],"pieces,":[88],"performs":[89],"parallel":[90],"each":[94],"piece,":[95],"then":[97],"merges":[98],"them":[99],"complete":[102],"design.":[103],"Evaluated":[104],"set":[107],"real":[109],"benchmarks,":[111],"reduces":[114],"by":[117,135],"more":[118],"than":[119],"50%":[120],"ensures":[122],"nearly":[123],"same":[125],"frequency":[127],"compared":[128],"provided":[134],"commercial":[137],"tool":[138],"Vivado.":[139]},"counts_by_year":[],"updated_date":"2026-04-17T18:11:37.981687","created_date":"2025-10-10T00:00:00"}
