{"id":"https://openalex.org/W2005778825","doi":"https://doi.org/10.1109/fccm.2014.51","title":"An Architectural Approach to Characterizing and Eliminating Sources of Inefficiency in a Soft Processor Design","display_name":"An Architectural Approach to Characterizing and Eliminating Sources of Inefficiency in a Soft Processor Design","publication_year":2014,"publication_date":"2014-05-01","ids":{"openalex":"https://openalex.org/W2005778825","doi":"https://doi.org/10.1109/fccm.2014.51","mag":"2005778825"},"language":"en","primary_location":{"id":"doi:10.1109/fccm.2014.51","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fccm.2014.51","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051051452","display_name":"Kaveh Aasaraai","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Kaveh Aasaraai","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Toronto, Toronto, ON, Canada","Electr. & Comput. Eng. Dept., Univ. of Toronto Toronto, Toronto, ON, Canada"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"Electr. & Comput. Eng. Dept., Univ. of Toronto Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072544251","display_name":"Andreas Moshovos","orcid":"https://orcid.org/0000-0001-7768-367X"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Andreas Moshovos","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Toronto, Toronto, ON, Canada","Electr. & Comput. Eng. Dept., Univ. of Toronto Toronto, Toronto, ON, Canada"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"Electr. & Comput. Eng. Dept., Univ. of Toronto Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5051051452"],"corresponding_institution_ids":["https://openalex.org/I185261750"],"apc_list":null,"apc_paid":null,"fwci":0.3065,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.57122583,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"169","last_page":"169"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9941999912261963,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7817209362983704},{"id":"https://openalex.org/keywords/stratix","display_name":"Stratix","score":0.7435422539710999},{"id":"https://openalex.org/keywords/processor-design","display_name":"Processor design","score":0.7242370247840881},{"id":"https://openalex.org/keywords/inefficiency","display_name":"Inefficiency","score":0.6832054853439331},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.6570404171943665},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.6545486450195312},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5744409561157227},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5584821701049805},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.5442765355110168},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5234619975090027},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5185344815254211},{"id":"https://openalex.org/keywords/modularity","display_name":"Modularity (biology)","score":0.46277913451194763},{"id":"https://openalex.org/keywords/pipeline-burst-cache","display_name":"Pipeline burst cache","score":0.4354773759841919},{"id":"https://openalex.org/keywords/application-specific-instruction-set-processor","display_name":"Application-specific instruction-set processor","score":0.4292571544647217},{"id":"https://openalex.org/keywords/branch-predictor","display_name":"Branch predictor","score":0.42378613352775574},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.41156119108200073},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.38015270233154297},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2397732436656952},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.12110486626625061}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7817209362983704},{"id":"https://openalex.org/C2776277307","wikidata":"https://www.wikidata.org/wiki/Q22074755","display_name":"Stratix","level":3,"score":0.7435422539710999},{"id":"https://openalex.org/C526435321","wikidata":"https://www.wikidata.org/wiki/Q1303814","display_name":"Processor design","level":2,"score":0.7242370247840881},{"id":"https://openalex.org/C2778869765","wikidata":"https://www.wikidata.org/wiki/Q6028363","display_name":"Inefficiency","level":2,"score":0.6832054853439331},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.6570404171943665},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.6545486450195312},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5744409561157227},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5584821701049805},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.5442765355110168},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5234619975090027},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5185344815254211},{"id":"https://openalex.org/C2779478453","wikidata":"https://www.wikidata.org/wiki/Q6889748","display_name":"Modularity (biology)","level":2,"score":0.46277913451194763},{"id":"https://openalex.org/C157547923","wikidata":"https://www.wikidata.org/wiki/Q7197276","display_name":"Pipeline burst cache","level":5,"score":0.4354773759841919},{"id":"https://openalex.org/C201736964","wikidata":"https://www.wikidata.org/wiki/Q621583","display_name":"Application-specific instruction-set processor","level":3,"score":0.4292571544647217},{"id":"https://openalex.org/C168522837","wikidata":"https://www.wikidata.org/wiki/Q679552","display_name":"Branch predictor","level":2,"score":0.42378613352775574},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41156119108200073},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.38015270233154297},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2397732436656952},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.12110486626625061},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C54355233","wikidata":"https://www.wikidata.org/wiki/Q7162","display_name":"Genetics","level":1,"score":0.0},{"id":"https://openalex.org/C175444787","wikidata":"https://www.wikidata.org/wiki/Q39072","display_name":"Microeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/fccm.2014.51","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fccm.2014.51","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines","raw_type":"proceedings-article"},{"id":"mag:2005778825","is_oa":false,"landing_page_url":"https://dblp.uni-trier.de/db/conf/fccm/fccm2014.html#AasaraaiM14","pdf_url":null,"source":{"id":"https://openalex.org/S4306418418","display_name":"Field-Programmable Custom Computing Machines","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":"Field-Programmable Custom Computing Machines","raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5400000214576721,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2157548138","https://openalex.org/W3049133399","https://openalex.org/W2140579965","https://openalex.org/W1676776177","https://openalex.org/W3126591632","https://openalex.org/W1969049073","https://openalex.org/W1032759598","https://openalex.org/W1608847703","https://openalex.org/W2135275335","https://openalex.org/W1603238397","https://openalex.org/W1591122270","https://openalex.org/W2098264320","https://openalex.org/W2144848513","https://openalex.org/W3200536684","https://openalex.org/W1991077993","https://openalex.org/W2349761828","https://openalex.org/W2161169297","https://openalex.org/W2542076870","https://openalex.org/W2547518970","https://openalex.org/W2159189019"],"abstract_inverted_index":{"This":[0],"work":[1],"takes":[2],"an":[3,31],"architectural":[4],"approach":[5],"to":[6,52,67],"systematically":[7,53],"characterize":[8,54],"components":[9],"and":[10,75,108,114],"mechanisms":[11],"that":[12,86,101,109],"are":[13],"the":[14,55,79],"main":[15],"sources":[16,56],"of":[17,57,71,116],"low":[18],"operating":[19],"clock":[20],"frequency":[21],"when":[22],"implementing":[23],"a":[24,44,50,64,96],"typical":[25,97],"pipelined":[26,99],"general":[27],"purpose":[28],"processor":[29,61],"on":[30,43,111],"FPGA.":[32],"Several":[33],"previous":[34],"works":[35],"have":[36],"addressed":[37],"specific":[38],"implementation":[39,73,107],"inefficiencies,":[40],"however":[41],"mostly":[42],"case-by-case":[45],"basis.":[46],"Accordingly.":[47],"there":[48],"is":[49,102],"need":[51],"inefficiency":[58],"in":[59],"soft":[60],"designs.":[62],"Such":[63],"characterization":[65],"serves":[66],"deepen":[68],"our":[69],"understanding":[70],"FPGA":[72],"trade-offs":[74],"can":[76],"serve":[77],"as":[78],"starting":[80],"point":[81],"for":[82,104],"developing":[83],"FPGA-friendly":[84],"designs":[85],"achieve":[87],"higher":[88],"performance":[89],"and/or":[90],"lower":[91],"area.":[92],"We":[93],"start":[94],"with":[95],"5-stage":[98],"architecture":[100],"optimized":[103],"custom":[105],"logic":[106],"focuses":[110],"correctness,":[112],"modularity,":[113],"speed":[115],"development.":[117]},"counts_by_year":[{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
