{"id":"https://openalex.org/W2493935358","doi":"https://doi.org/10.1109/esscirc.2016.7598292","title":"DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment","display_name":"DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment","publication_year":2016,"publication_date":"2016-09-01","ids":{"openalex":"https://openalex.org/W2493935358","doi":"https://doi.org/10.1109/esscirc.2016.7598292","mag":"2493935358"},"language":"en","primary_location":{"id":"doi:10.1109/esscirc.2016.7598292","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2016.7598292","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://infoscience.epfl.ch/record/218771","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111593170","display_name":"Jeremy Constantin","orcid":null},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":true,"raw_author_name":"Jeremy Constantin","raw_affiliation_strings":["Telecommunications Circuits Laboratory (TCL), \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Switzerland"],"affiliations":[{"raw_affiliation_string":"Telecommunications Circuits Laboratory (TCL), \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078908633","display_name":"Andrea Bonetti","orcid":"https://orcid.org/0000-0002-0135-5095"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Andrea Bonetti","raw_affiliation_strings":["Telecommunications Circuits Laboratory (TCL), \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Switzerland"],"affiliations":[{"raw_affiliation_string":"Telecommunications Circuits Laboratory (TCL), \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026444183","display_name":"Adam Teman","orcid":"https://orcid.org/0000-0002-8233-4711"},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]},{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH","IL"],"is_corresponding":false,"raw_author_name":"Adam Teman","raw_affiliation_strings":["Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel","Telecommunications Circuits Laboratory (TCL), \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Switzerland"],"affiliations":[{"raw_affiliation_string":"Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel","institution_ids":["https://openalex.org/I13955877"]},{"raw_affiliation_string":"Telecommunications Circuits Laboratory (TCL), \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090996622","display_name":"Christoph Muller","orcid":null},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Christoph Muller","raw_affiliation_strings":["Telecommunications Circuits Laboratory (TCL), \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Switzerland"],"affiliations":[{"raw_affiliation_string":"Telecommunications Circuits Laboratory (TCL), \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037553832","display_name":"Lorenz Schmid","orcid":"https://orcid.org/0000-0003-0889-7767"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Lorenz Schmid","raw_affiliation_strings":["Telecommunications Circuits Laboratory (TCL), \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Switzerland"],"affiliations":[{"raw_affiliation_string":"Telecommunications Circuits Laboratory (TCL), \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059133771","display_name":"Andreas Burg","orcid":"https://orcid.org/0000-0002-7270-5558"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Andreas Burg","raw_affiliation_strings":["Telecommunications Circuits Laboratory (TCL), \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Switzerland"],"affiliations":[{"raw_affiliation_string":"Telecommunications Circuits Laboratory (TCL), \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Switzerland","institution_ids":["https://openalex.org/I5124864"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5111593170"],"corresponding_institution_ids":["https://openalex.org/I5124864"],"apc_list":null,"apc_paid":null,"fwci":2.2473,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.87335646,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"261","last_page":"264"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.7688757181167603},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.733466386795044},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.6919333934783936},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6722115278244019},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.6505611538887024},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.6276952028274536},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.5928839445114136},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.5600554943084717},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.5595330595970154},{"id":"https://openalex.org/keywords/glitch","display_name":"Glitch","score":0.5448103547096252},{"id":"https://openalex.org/keywords/32-bit","display_name":"32-bit","score":0.5398961305618286},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.469537615776062},{"id":"https://openalex.org/keywords/instructions-per-cycle","display_name":"Instructions per cycle","score":0.4499111473560333},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.4492081105709076},{"id":"https://openalex.org/keywords/silicon-on-insulator","display_name":"Silicon on insulator","score":0.4167616367340088},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.35884660482406616},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.33811259269714355},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.31102168560028076},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.31025177240371704},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.2833141088485718},{"id":"https://openalex.org/keywords/central-processing-unit","display_name":"Central processing unit","score":0.246387779712677},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.11705264449119568},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.08562520146369934},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08528327941894531},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.08116534352302551},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07616350054740906}],"concepts":[{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.7688757181167603},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.733466386795044},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.6919333934783936},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6722115278244019},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.6505611538887024},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.6276952028274536},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.5928839445114136},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.5600554943084717},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.5595330595970154},{"id":"https://openalex.org/C191287063","wikidata":"https://www.wikidata.org/wiki/Q543281","display_name":"Glitch","level":3,"score":0.5448103547096252},{"id":"https://openalex.org/C75695347","wikidata":"https://www.wikidata.org/wiki/Q225147","display_name":"32-bit","level":2,"score":0.5398961305618286},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.469537615776062},{"id":"https://openalex.org/C156972235","wikidata":"https://www.wikidata.org/wiki/Q1443434","display_name":"Instructions per cycle","level":3,"score":0.4499111473560333},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.4492081105709076},{"id":"https://openalex.org/C53143962","wikidata":"https://www.wikidata.org/wiki/Q1478788","display_name":"Silicon on insulator","level":3,"score":0.4167616367340088},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.35884660482406616},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.33811259269714355},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.31102168560028076},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.31025177240371704},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.2833141088485718},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.246387779712677},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.11705264449119568},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.08562520146369934},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08528327941894531},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.08116534352302551},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07616350054740906},{"id":"https://openalex.org/C94915269","wikidata":"https://www.wikidata.org/wiki/Q1834857","display_name":"Detector","level":2,"score":0.0},{"id":"https://openalex.org/C544956773","wikidata":"https://www.wikidata.org/wiki/Q670","display_name":"Silicon","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/esscirc.2016.7598292","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2016.7598292","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","raw_type":"proceedings-article"},{"id":"pmh:oai:infoscience.epfl.ch:218771","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/218771","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"}],"best_oa_location":{"id":"pmh:oai:infoscience.epfl.ch:218771","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/218771","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8999999761581421,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1911029421","https://openalex.org/W1991670063","https://openalex.org/W2020875745","https://openalex.org/W2077338724","https://openalex.org/W2104677471","https://openalex.org/W2178304595","https://openalex.org/W2289333215","https://openalex.org/W2293806773","https://openalex.org/W2505856658","https://openalex.org/W4236432903","https://openalex.org/W4242565052","https://openalex.org/W6640006728","https://openalex.org/W6655872142","https://openalex.org/W6725064940"],"related_works":["https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W4247089581","https://openalex.org/W2040807843","https://openalex.org/W2559451387","https://openalex.org/W3006003651","https://openalex.org/W2163637408","https://openalex.org/W2107880456","https://openalex.org/W4231008241","https://openalex.org/W2493935358"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"DynOR,":[3],"a":[4,31,50,66,92,99,125,134],"32-bit":[5],"6-stage":[6],"Open-RISC":[7],"microprocessor":[8],"with":[9,69,98],"dynamic":[10,19],"clock":[11,23,53,63],"adjustment.":[12],"To":[13,45],"alleviate":[14],"the":[15,22,26,36,43,62,120],"issue":[16],"of":[17,25,57,61,86,95,105],"unused":[18],"timing":[20],"margins,":[21],"period":[24,64],"processor":[27],"is":[28],"adjusted":[29],"on":[30,35,139],"cycle-by-cycle":[32],"level,":[33],"based":[34,138],"instruction":[37],"types":[38],"currently":[39],"in":[40,42,75,88],"flight":[41],"pipeline.":[44],"this":[46,110],"end,":[47],"we":[48],"employ":[49],"custom":[51],"designed":[52],"generation":[54],"unit,":[55],"capable":[56],"immediate":[58],"glitch-free":[59],"adjustments":[60],"over":[65,91],"wide":[67,93],"range":[68,94],"fine":[70],"granularity.":[71],"Our":[72],"chip":[73,121],"measurements":[74],"28nm":[76],"FD-SOI":[77],"technology":[78],"show":[79],"that":[80],"DynOR":[81],"provides":[82],"an":[83],"average":[84],"speedup":[85,101,111],"19%":[87],"program":[89],"execution":[90],"operating":[96],"conditions,":[97],"peak":[100],"for":[102,124],"certain":[103],"applications":[104],"up":[106,129],"to":[107,118,130,133],"41%.":[108],"Furthermore,":[109],"can":[112],"be":[113],"traded":[114],"off":[115],"against":[116],"energy,":[117],"reduce":[119],"power":[122],"consumption":[123],"typical":[126],"die":[127],"by":[128],"15%,":[131],"compared":[132],"static":[135],"clocking":[136],"scheme":[137],"worst":[140],"case":[141],"excitation.":[142]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}