{"id":"https://openalex.org/W2114655921","doi":"https://doi.org/10.1109/esscirc.2009.5326028","title":"Power reduction techniques for an 8-core xeon<sup>®</sup> processor","display_name":"Power reduction techniques for an 8-core xeon<sup>®</sup> processor","publication_year":2009,"publication_date":"2009-09-01","ids":{"openalex":"https://openalex.org/W2114655921","doi":"https://doi.org/10.1109/esscirc.2009.5326028","mag":"2114655921"},"language":"en","primary_location":{"id":"doi:10.1109/esscirc.2009.5326028","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2009.5326028","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 Proceedings of ESSCIRC","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037919423","display_name":"Stefan Rusu","orcid":"https://orcid.org/0000-0002-3322-9173"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Stefan Rusu","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA","Intel Corp., Santa Clara, CA, , USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corp., Santa Clara, CA, , USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036660816","display_name":"Simon Tam","orcid":"https://orcid.org/0000-0003-3918-7100"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Simon Tam","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA","Intel Corp., Santa Clara, CA, , USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corp., Santa Clara, CA, , USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032763051","display_name":"H. Muljono","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Harry Muljono","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA","Intel Corp., Santa Clara, CA, , USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corp., Santa Clara, CA, , USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012306013","display_name":"Jason Stinson","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jason Stinson","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA","Intel Corp., Santa Clara, CA, , USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corp., Santa Clara, CA, , USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066738995","display_name":"D. Ayers","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Ayers","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA","Intel Corp., Santa Clara, CA, , USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corp., Santa Clara, CA, , USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108484112","display_name":"Jonathan Chang","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jonathan Chang","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA","Intel Corp., Santa Clara, CA, , USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corp., Santa Clara, CA, , USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024681582","display_name":"Raj Varada","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Raj Varada","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA","Intel Corp., Santa Clara, CA, , USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corp., Santa Clara, CA, , USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068113720","display_name":"Matt Ratta","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Matt Ratta","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA","Intel Corp., Santa Clara, CA, , USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corp., Santa Clara, CA, , USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042497106","display_name":"Sailesh Kottapalli","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sailesh Kottapalli","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA","Intel Corp., Santa Clara, CA, , USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corp., Santa Clara, CA, , USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108618300","display_name":"Sujal Vora","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sujal Vora","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA","Intel Corp., Santa Clara, CA, , USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corp., Santa Clara, CA, , USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":10,"corresponding_author_ids":["https://openalex.org/A5037919423"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":2.0935,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.8770006,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"340","last_page":"343"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.7927300930023193},{"id":"https://openalex.org/keywords/idle","display_name":"Idle","score":0.7878608703613281},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.7564023733139038},{"id":"https://openalex.org/keywords/power-management","display_name":"Power management","score":0.5236720442771912},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.511845052242279},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5099338293075562},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.506194531917572},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5030454993247986},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.48568591475486755},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4529988169670105},{"id":"https://openalex.org/keywords/voltage-regulator","display_name":"Voltage regulator","score":0.41152793169021606},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4077743887901306},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3817445635795593},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3692328929901123},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.35751408338546753},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.24805700778961182},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.23727738857269287},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.22673815488815308},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.17402103543281555},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.15762311220169067},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.10938647389411926},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.09808295965194702}],"concepts":[{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.7927300930023193},{"id":"https://openalex.org/C16320812","wikidata":"https://www.wikidata.org/wiki/Q1812200","display_name":"Idle","level":2,"score":0.7878608703613281},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.7564023733139038},{"id":"https://openalex.org/C2778774385","wikidata":"https://www.wikidata.org/wiki/Q4437810","display_name":"Power management","level":3,"score":0.5236720442771912},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.511845052242279},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5099338293075562},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.506194531917572},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5030454993247986},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.48568591475486755},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4529988169670105},{"id":"https://openalex.org/C110706871","wikidata":"https://www.wikidata.org/wiki/Q851210","display_name":"Voltage regulator","level":3,"score":0.41152793169021606},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4077743887901306},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3817445635795593},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3692328929901123},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.35751408338546753},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.24805700778961182},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.23727738857269287},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.22673815488815308},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.17402103543281555},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.15762311220169067},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.10938647389411926},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.09808295965194702},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/esscirc.2009.5326028","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2009.5326028","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 Proceedings of ESSCIRC","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2001894083","https://openalex.org/W2096046678","https://openalex.org/W2104196799","https://openalex.org/W2126898248","https://openalex.org/W3148024018","https://openalex.org/W6650975361"],"related_works":["https://openalex.org/W3127845477","https://openalex.org/W2938543345","https://openalex.org/W2421981162","https://openalex.org/W1583123542","https://openalex.org/W2052583367","https://openalex.org/W2102121056","https://openalex.org/W39641061","https://openalex.org/W2114655921","https://openalex.org/W2130965751","https://openalex.org/W4247326638"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"the":[3,10,52,89,97,102],"power":[4,25,58,61,78,83,103],"reduction":[5],"and":[6,18,30,40,46,57,71,79,93],"management":[7],"techniques":[8],"for":[9],"45":[11],"nm,":[12],"8-core":[13],"Nehalem-EX":[14],"processor.":[15],"Multiple":[16],"clock":[17],"voltage":[19,70,98],"domains":[20],"are":[21,34],"used":[22,35],"to":[23,36,100],"reduce":[24],"consumption.":[26],"Long":[27],"channel":[28],"devices":[29],"cache":[31,41],"sleep":[32],"mode":[33],"minimize":[37,60],"leakage.":[38],"Core":[39],"recovery":[42],"improve":[43,101],"manufacturing":[44],"yields":[45],"enable":[47],"multiple":[48],"product":[49],"flavors":[50],"from":[51],"same":[53],"silicon":[54],"die.":[55],"Clock":[56],"gating":[59],"consumed":[62],"by":[63,86],"disabled":[64],"blocks.":[65],"An":[66],"on-die":[67],"microcontroller":[68],"manages":[69],"frequency":[72],"operating":[73],"points,":[74],"as":[75,77],"well":[76],"thermal":[80],"events.":[81],"Idle":[82],"is":[84],"reduced":[85],"shutting":[87],"off":[88],"un-terminated":[90],"I/O":[91],"links":[92],"shedding":[94],"phases":[95],"in":[96],"regulator":[99],"conversion":[104],"efficiency.":[105]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}