{"id":"https://openalex.org/W2099245737","doi":"https://doi.org/10.1109/esscirc.2008.4681789","title":"Experimental assessment of logic circuit performance variability with regular fabrics at 90nm technology node","display_name":"Experimental assessment of logic circuit performance variability with regular fabrics at 90nm technology node","publication_year":2008,"publication_date":"2008-09-01","ids":{"openalex":"https://openalex.org/W2099245737","doi":"https://doi.org/10.1109/esscirc.2008.4681789","mag":"2099245737"},"language":"en","primary_location":{"id":"doi:10.1109/esscirc.2008.4681789","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2008.4681789","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2008 - 34th European Solid-State Circuits Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103719754","display_name":"Sungdae Choi","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Sungdae Choi","raw_affiliation_strings":["University of Tokyo, Japan","University of Tokyo, Tokyo,"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"University of Tokyo, Tokyo,","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111992985","display_name":"Katsuyuki Ikeuchi","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Katsuyuki Ikeuchi","raw_affiliation_strings":["University of Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100710096","display_name":"Hyun-Kyung Kim","orcid":"https://orcid.org/0000-0002-2528-6231"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hyunkyung Kim","raw_affiliation_strings":["University of Tokyo, Japan","University of Tokyo, Tokyo,"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"University of Tokyo, Tokyo,","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109094304","display_name":"Kenichi Inagaki","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kenichi Inagaki","raw_affiliation_strings":["University of Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113697147","display_name":"M. Murakata","orcid":null},"institutions":[{"id":"https://openalex.org/I4210125918","display_name":"Semiconductor Energy Laboratory (Japan)","ror":"https://ror.org/02vszc135","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210125918"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masami Murakata","raw_affiliation_strings":["Semiconductor Technology Academic Research Center, Japan"],"affiliations":[{"raw_affiliation_string":"Semiconductor Technology Academic Research Center, Japan","institution_ids":["https://openalex.org/I4210125918"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057068098","display_name":"Nobuyuki Nishiguchi","orcid":null},"institutions":[{"id":"https://openalex.org/I4210125918","display_name":"Semiconductor Energy Laboratory (Japan)","ror":"https://ror.org/02vszc135","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210125918"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Nobuyuki Nishiguchi","raw_affiliation_strings":["Semiconductor Technology Academic Research Center, Japan"],"affiliations":[{"raw_affiliation_string":"Semiconductor Technology Academic Research Center, Japan","institution_ids":["https://openalex.org/I4210125918"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003282110","display_name":"Makoto Takamiya","orcid":"https://orcid.org/0000-0003-0289-7790"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Makoto Takamiya","raw_affiliation_strings":["University of Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112189116","display_name":"Takayasu Sakurai","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Takayasu Sakurai","raw_affiliation_strings":["University of Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5103719754"],"corresponding_institution_ids":["https://openalex.org/I74801974"],"apc_list":null,"apc_paid":null,"fwci":0.339,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.65067402,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"50","last_page":"53"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.6771007180213928},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6189104318618774},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5521883368492126},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5462722778320312},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5448264479637146},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5377492904663086},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5280906558036804},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5232947468757629},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.4499529004096985},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.44109055399894714},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.39928656816482544},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.23400861024856567},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2175142467021942},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.13773450255393982},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07288423180580139}],"concepts":[{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.6771007180213928},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6189104318618774},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5521883368492126},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5462722778320312},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5448264479637146},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5377492904663086},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5280906558036804},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5232947468757629},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.4499529004096985},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.44109055399894714},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.39928656816482544},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.23400861024856567},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2175142467021942},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.13773450255393982},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07288423180580139},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/esscirc.2008.4681789","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2008.4681789","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2008 - 34th European Solid-State Circuits Conference","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.689.3335","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.689.3335","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://icdesign.iis.u-tokyo.ac.jp/2008_19.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1572287951","https://openalex.org/W1967616151","https://openalex.org/W1971495518","https://openalex.org/W2033443176","https://openalex.org/W2042809000","https://openalex.org/W2100344939","https://openalex.org/W2125952738","https://openalex.org/W2134849712","https://openalex.org/W2140823559","https://openalex.org/W6643197073"],"related_works":["https://openalex.org/W2789662562","https://openalex.org/W1966764473","https://openalex.org/W1553855433","https://openalex.org/W2017528947","https://openalex.org/W2066518505","https://openalex.org/W2102499515","https://openalex.org/W2098419840","https://openalex.org/W2121963733","https://openalex.org/W1977171228","https://openalex.org/W2170504327"],"abstract_inverted_index":{"Regular":[0],"fabric":[1],"structure":[2,82,93],"is":[3,63,68,94],"expected":[4],"to":[5],"reduce":[6],"the":[7,12,23,26,54,59,80,87,91,98],"process":[8,74],"variations":[9,62],"and":[10,53,75,86],"increase":[11],"yield":[13],"in":[14],"sub-micron":[15],"technology":[16],"regime.":[17],"Few":[18],"experimental":[19],"assessments,":[20],"however,":[21],"for":[22],"effectiveness":[24],"of":[25,39,47,56,90,101],"regular":[27,81,92],"structures":[28],"has":[29],"been":[30],"carried":[31],"out":[32],"yet.":[33],"In":[34],"this":[35],"paper,":[36],"three":[37],"kinds":[38,46],"circuit":[40,60],"blocks":[41],"are":[42],"implemented":[43],"with":[44,50,70,104],"four":[45],"layout":[48],"styles":[49],"different":[51],"regularity,":[52],"effect":[55],"regularity":[57],"on":[58],"performance":[61],"evaluated.":[64],"A":[65],"test":[66],"chip":[67],"fabricated":[69],"90nm":[71],"CMOS":[72],"logic":[73],"measured":[76],"results":[77],"show":[78],"that":[79],"increases":[83],"average":[84],"delay,":[85],"worst":[88,99],"delay":[89,100],"not":[95],"better":[96],"than":[97],"normal":[102],"circuits":[103],"irregular":[105],"standard":[106],"cells.":[107]},"counts_by_year":[{"year":2016,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}