{"id":"https://openalex.org/W1971359408","doi":"https://doi.org/10.1109/emeit.2011.6023995","title":"The design and simulation of array multiplier improved with pipeline techniques","display_name":"The design and simulation of array multiplier improved with pipeline techniques","publication_year":2011,"publication_date":"2011-08-01","ids":{"openalex":"https://openalex.org/W1971359408","doi":"https://doi.org/10.1109/emeit.2011.6023995","mag":"1971359408"},"language":"en","primary_location":{"id":"doi:10.1109/emeit.2011.6023995","is_oa":false,"landing_page_url":"https://doi.org/10.1109/emeit.2011.6023995","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of 2011 International Conference on Electronic & Mechanical Engineering and Information Technology","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5058120421","display_name":"Zhong-ye Yang","orcid":null},"institutions":[{"id":"https://openalex.org/I308837","display_name":"Suzhou University of Science and Technology","ror":"https://ror.org/04en8wb91","country_code":"CN","type":"education","lineage":["https://openalex.org/I308837"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Zhong-ye Yang","raw_affiliation_strings":["Dept. of Electronics and Information Engineering, Suzhou University of Science and Technology, Suzhou, Jiangsu, China"],"affiliations":[{"raw_affiliation_string":"Dept. of Electronics and Information Engineering, Suzhou University of Science and Technology, Suzhou, Jiangsu, China","institution_ids":["https://openalex.org/I308837"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5088142878","display_name":"Jinqiu Xiao","orcid":null},"institutions":[{"id":"https://openalex.org/I308837","display_name":"Suzhou University of Science and Technology","ror":"https://ror.org/04en8wb91","country_code":"CN","type":"education","lineage":["https://openalex.org/I308837"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jin-qiu Xiao","raw_affiliation_strings":["Dept. of Electronics and Information Engineering, Suzhou University of Science and Technology, Suzhou, Jiangsu, China"],"affiliations":[{"raw_affiliation_string":"Dept. of Electronics and Information Engineering, Suzhou University of Science and Technology, Suzhou, Jiangsu, China","institution_ids":["https://openalex.org/I308837"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5058120421"],"corresponding_institution_ids":["https://openalex.org/I308837"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.05662514,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"4326","last_page":"4329"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.710502028465271},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6744974255561829},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.6700708270072937},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.571588397026062},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.38869303464889526},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.30362313985824585},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.15951716899871826},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1558447778224945}],"concepts":[{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.710502028465271},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6744974255561829},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.6700708270072937},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.571588397026062},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.38869303464889526},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.30362313985824585},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.15951716899871826},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1558447778224945},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/emeit.2011.6023995","is_oa":false,"landing_page_url":"https://doi.org/10.1109/emeit.2011.6023995","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of 2011 International Conference on Electronic & Mechanical Engineering and Information Technology","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2149444980","https://openalex.org/W2166567121"],"related_works":["https://openalex.org/W2383333355","https://openalex.org/W2144353363","https://openalex.org/W2389325540","https://openalex.org/W3011158618","https://openalex.org/W2381710881","https://openalex.org/W316086783","https://openalex.org/W2377412115","https://openalex.org/W567982934","https://openalex.org/W2378016457","https://openalex.org/W2355563154"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"the":[3,16,22,33,43],"time":[4],"complexity":[5],"of":[6,24,35,45],"two's":[7],"complement":[8],"Array":[9,25],"Multiplier":[10,26],"has":[11,29,37,50],"been":[12,30,38,51],"analyzed.":[13],"Based":[14],"on":[15],"analysis,":[17],"a":[18],"method":[19],"for":[20],"improving":[21],"performance":[23],"with":[27,40],"pipeline":[28],"discussed,":[31],"and":[32,47],"modeling":[34],"it":[36],"built":[39],"VHDL.":[41],"Furthermore,":[42],"conclusion":[44],"Simulation":[46],"function":[48],"verification":[49],"given.":[52]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}