{"id":"https://openalex.org/W4417169681","doi":"https://doi.org/10.1109/dsd67783.2025.00040","title":"Designing Energy-Efficient Approximate Circuits for the FPGA Technology","display_name":"Designing Energy-Efficient Approximate Circuits for the FPGA Technology","publication_year":2025,"publication_date":"2025-09-10","ids":{"openalex":"https://openalex.org/W4417169681","doi":"https://doi.org/10.1109/dsd67783.2025.00040"},"language":null,"primary_location":{"id":"doi:10.1109/dsd67783.2025.00040","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd67783.2025.00040","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 28th Euromicro Conference on Digital System Design (DSD)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5040622270","display_name":"Mario Barbareschi","orcid":"https://orcid.org/0000-0002-1417-6328"},"institutions":[{"id":"https://openalex.org/I4210117450","display_name":"Federico II University Hospital","ror":"https://ror.org/02jr6tp70","country_code":"IT","type":"healthcare","lineage":["https://openalex.org/I4210117450","https://openalex.org/I71267560"]},{"id":"https://openalex.org/I71267560","display_name":"University of Naples Federico II","ror":"https://ror.org/05290cv24","country_code":"IT","type":"education","lineage":["https://openalex.org/I71267560"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Mario Barbareschi","raw_affiliation_strings":["University of Naples Federico II Naples,Department of Electrical Engineering and Information Technologies,Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Naples Federico II Naples,Department of Electrical Engineering and Information Technologies,Italy","institution_ids":["https://openalex.org/I4210117450","https://openalex.org/I71267560"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089194416","display_name":"Salvatore Barone","orcid":"https://orcid.org/0000-0003-2007-3744"},"institutions":[{"id":"https://openalex.org/I4210125310","display_name":"Pegaso University","ror":"https://ror.org/03cxwg632","country_code":"IT","type":"education","lineage":["https://openalex.org/I4210125310"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Salvatore Barone","raw_affiliation_strings":["Pegaso University,Department of Computer Science and Technologies,Naples,Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Pegaso University,Department of Computer Science and Technologies,Naples,Italy","institution_ids":["https://openalex.org/I4210125310"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045567395","display_name":"Nicola Mazzocca","orcid":"https://orcid.org/0000-0002-0401-9687"},"institutions":[{"id":"https://openalex.org/I4210117450","display_name":"Federico II University Hospital","ror":"https://ror.org/02jr6tp70","country_code":"IT","type":"healthcare","lineage":["https://openalex.org/I4210117450","https://openalex.org/I71267560"]},{"id":"https://openalex.org/I71267560","display_name":"University of Naples Federico II","ror":"https://ror.org/05290cv24","country_code":"IT","type":"education","lineage":["https://openalex.org/I71267560"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Nicola Mazzocca","raw_affiliation_strings":["University of Naples Federico II Naples,Department of Electrical Engineering and Information Technologies,Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Naples Federico II Naples,Department of Electrical Engineering and Information Technologies,Italy","institution_ids":["https://openalex.org/I4210117450","https://openalex.org/I71267560"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5054341978","display_name":"Alberto Moriconi","orcid":"https://orcid.org/0000-0001-9275-4608"},"institutions":[{"id":"https://openalex.org/I4210117450","display_name":"Federico II University Hospital","ror":"https://ror.org/02jr6tp70","country_code":"IT","type":"healthcare","lineage":["https://openalex.org/I4210117450","https://openalex.org/I71267560"]},{"id":"https://openalex.org/I71267560","display_name":"University of Naples Federico II","ror":"https://ror.org/05290cv24","country_code":"IT","type":"education","lineage":["https://openalex.org/I71267560"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Alberto Moriconi","raw_affiliation_strings":["University of Naples Federico II Naples,Department of Electrical Engineering and Information Technologies,Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Naples Federico II Naples,Department of Electrical Engineering and Information Technologies,Italy","institution_ids":["https://openalex.org/I4210117450","https://openalex.org/I71267560"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.48230049,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"214","last_page":"223"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.6599000096321106,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.6599000096321106,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.1565999984741211,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.09120000153779984,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7368000149726868},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5892000198364258},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.583899974822998},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5774999856948853},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.5622000098228455},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.4708000123500824},{"id":"https://openalex.org/keywords/representation","display_name":"Representation (politics)","score":0.453000009059906},{"id":"https://openalex.org/keywords/fidelity","display_name":"Fidelity","score":0.43459999561309814},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.39640000462532043},{"id":"https://openalex.org/keywords/field","display_name":"Field (mathematics)","score":0.3799000084400177}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7368000149726868},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7319999933242798},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5892000198364258},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.583899974822998},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5774999856948853},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.5622000098228455},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.546500027179718},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.4708000123500824},{"id":"https://openalex.org/C2776359362","wikidata":"https://www.wikidata.org/wiki/Q2145286","display_name":"Representation (politics)","level":3,"score":0.453000009059906},{"id":"https://openalex.org/C2776459999","wikidata":"https://www.wikidata.org/wiki/Q2119376","display_name":"Fidelity","level":2,"score":0.43459999561309814},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.39640000462532043},{"id":"https://openalex.org/C9652623","wikidata":"https://www.wikidata.org/wiki/Q190109","display_name":"Field (mathematics)","level":2,"score":0.3799000084400177},{"id":"https://openalex.org/C45235069","wikidata":"https://www.wikidata.org/wiki/Q278425","display_name":"Table (database)","level":2,"score":0.3783000111579895},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.36660000681877136},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3465999960899353},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.3310000002384186},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33059999346733093},{"id":"https://openalex.org/C113364801","wikidata":"https://www.wikidata.org/wiki/Q26674","display_name":"High fidelity","level":2,"score":0.32760000228881836},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.32350000739097595},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.3222000002861023},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.31700000166893005},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3138999938964844},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.3122999966144562},{"id":"https://openalex.org/C126042441","wikidata":"https://www.wikidata.org/wiki/Q1324888","display_name":"Frame (networking)","level":2,"score":0.3057999908924103},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.29910001158714294},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.28029999136924744},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.2718999981880188},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.27000001072883606},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.2644999921321869},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.26159998774528503},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.25999999046325684},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2549999952316284}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dsd67783.2025.00040","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd67783.2025.00040","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 28th Euromicro Conference on Digital System Design (DSD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":38,"referenced_works":["https://openalex.org/W1998305460","https://openalex.org/W2010867627","https://openalex.org/W2079170559","https://openalex.org/W2100465945","https://openalex.org/W2104492856","https://openalex.org/W2126105956","https://openalex.org/W2147800946","https://openalex.org/W2194775991","https://openalex.org/W2244005500","https://openalex.org/W2496519511","https://openalex.org/W2612139336","https://openalex.org/W2738060292","https://openalex.org/W2740157106","https://openalex.org/W2799036754","https://openalex.org/W2808908725","https://openalex.org/W2895540242","https://openalex.org/W2903054571","https://openalex.org/W2903222888","https://openalex.org/W2958306322","https://openalex.org/W2980235527","https://openalex.org/W2996685260","https://openalex.org/W3018203643","https://openalex.org/W3126267573","https://openalex.org/W3128386784","https://openalex.org/W3146543203","https://openalex.org/W3155323635","https://openalex.org/W3166637233","https://openalex.org/W3195784889","https://openalex.org/W4210659427","https://openalex.org/W4211125327","https://openalex.org/W4220829081","https://openalex.org/W4225500326","https://openalex.org/W4229450561","https://openalex.org/W4233469764","https://openalex.org/W4235991875","https://openalex.org/W4285199350","https://openalex.org/W4285239639","https://openalex.org/W4392919679"],"related_works":[],"abstract_inverted_index":{"A":[0],"significant":[1,209],"number":[2],"of":[3,18,64,166],"contributions":[4],"focusing":[5],"on":[6,74,99],"approximation":[7,67],"techniques":[8,36,68],"for":[9,146,193,204,220],"Application":[10],"Specific":[11],"Integrated":[12],"Circuits":[13],"(ASIC)":[14],"has":[15],"become":[16],"part":[17],"the":[19,55,59,65,105,112,150,178,182,197,208,227],"scientific":[20],"literature.":[21],"Conversely,":[22],"Field":[23],"Programmable":[24],"Gate":[25],"Arrays":[26],"(FPGAs)":[27],"are":[28,78,116,202],"often":[29,39],"overlooked,":[30],"despite":[31],"their":[32],"increasing":[33],"spread.":[34],"ASIC-based":[35],"are,":[37],"however,":[38],"unsuitable":[40],"when":[41,124],"it":[42],"comes":[43],"to":[44,54,93,103,119,141,172,176,214],"FPGA,":[45],"providing":[46],"little":[47,125],"or":[48,77,90,121,126],"no":[49,127],"advantages":[50],"at":[51],"all,":[52],"due":[53],"inherent":[56],"differences":[57],"in":[58,157,162],"two":[60],"target":[61],"technologies.":[62],"Most":[63],"FPGA-based":[66],"being":[69],"recently":[70],"proposed":[71],"either":[72],"rely":[73,98],"manual":[75],"approximation,":[76],"too":[79],"tightly":[80],"coupled":[81],"with":[82],"a":[83,137],"particular":[84],"FPGA":[85,158],"fabric,":[86],"making":[87],"them":[88],"ineffective":[89],"even":[91,122],"inapplicable":[92],"other":[94],"devices.":[95],"Furthermore,":[96],"they":[97],"machine-learning":[100,190],"based":[101,191],"predictors":[102,192],"drive":[104],"Design":[106],"Space":[107],"Exploration":[108],"(DSE),":[109],"that,":[110],"given":[111],"high":[113],"fidelity":[114],"required,":[115],"usually":[117],"burdensome":[118],"achieve,":[120],"unfeasible":[123],"training":[128],"data":[129],"is":[130,218],"available.":[131],"In":[132],"this":[133],"paper,":[134],"we":[135,170],"discuss":[136],"fabricand":[138],"workload-independent":[139],"approach":[140,217],"design":[142,224],"power-optimized":[143],"approximate":[144,222],"circuits":[145,201],"FPGA.":[147,228],"We":[148],"exploit":[149],"existing":[151],"bond":[152],"between":[153],"Look-Up":[154],"Table":[155],"(LUT)-mapping":[156],"synthesis":[159,186],"and":[160,169,207],"cut-enumeration":[161],"And-Inverter":[163],"graph":[164],"representation":[165],"digital":[167],"circuits,":[168],"resort":[171],"an":[173],"analytical":[174],"model":[175],"estimate":[177],"power":[179],"consumption":[180],"during":[181,196],"DSE,":[183],"avoiding":[184],"costly":[185],"as":[187,189],"well":[188],"hardware":[194],"resources":[195],"DSE.":[198],"Several":[199],"benchmark":[200],"considered":[203],"evaluation":[205],"purposes,":[206],"savings":[210],"achieved":[211],"allow":[212],"us":[213],"claim":[215],"our":[216],"suitable":[219],"addressing":[221],"circuit":[223],"while":[225],"targeting":[226]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-12-09T00:00:00"}