{"id":"https://openalex.org/W2479378865","doi":"https://doi.org/10.1109/dsd.2017.31","title":"Automatic Control Flow Generation for OpenVX Graphs","display_name":"Automatic Control Flow Generation for OpenVX Graphs","publication_year":2017,"publication_date":"2017-08-01","ids":{"openalex":"https://openalex.org/W2479378865","doi":"https://doi.org/10.1109/dsd.2017.31","mag":"2479378865"},"language":"en","primary_location":{"id":"doi:10.1109/dsd.2017.31","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2017.31","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 Euromicro Conference on Digital System Design (DSD)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5004494251","display_name":"Merten Popp","orcid":"https://orcid.org/0000-0001-5916-8180"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Merten Popp","raw_affiliation_strings":["Intel Corporation, Eindhoven, The Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Eindhoven, The Netherlands","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067064119","display_name":"Stef Van Son","orcid":null},"institutions":[{"id":"https://openalex.org/I83019370","display_name":"Eindhoven University of Technology","ror":"https://ror.org/02c2kyt77","country_code":"NL","type":"education","lineage":["https://openalex.org/I83019370"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Stef Van Son","raw_affiliation_strings":["Eindhoven University of Technology, Eindhoven, Noord-Brabant, NL"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Eindhoven University of Technology, Eindhoven, Noord-Brabant, NL","institution_ids":["https://openalex.org/I83019370"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5104101757","display_name":"Orlando Moreira","orcid":"https://orcid.org/0000-0003-2362-4169"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Orlando Moreira","raw_affiliation_strings":["Intel Corporation, Eindhoven, The Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Eindhoven, The Netherlands","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.1884,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.29820225,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"198","last_page":"204"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.9727077484130859},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.836438775062561},{"id":"https://openalex.org/keywords/control-flow","display_name":"Control flow","score":0.6157482862472534},{"id":"https://openalex.org/keywords/data-flow-analysis","display_name":"Data-flow analysis","score":0.5878005027770996},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.5526161193847656},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.5409953594207764},{"id":"https://openalex.org/keywords/data-flow-diagram","display_name":"Data flow diagram","score":0.5305379033088684},{"id":"https://openalex.org/keywords/heuristic","display_name":"Heuristic","score":0.5059186816215515},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.48545652627944946},{"id":"https://openalex.org/keywords/limiting","display_name":"Limiting","score":0.46815255284309387},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.4599233567714691},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.45569270849227905},{"id":"https://openalex.org/keywords/control-flow-graph","display_name":"Control flow graph","score":0.4540678858757019},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.45180052518844604},{"id":"https://openalex.org/keywords/graph-reduction","display_name":"Graph reduction","score":0.4300358295440674},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3480353057384491},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3448742628097534},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.32682955265045166},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.2025536298751831},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.10828804969787598},{"id":"https://openalex.org/keywords/functional-programming","display_name":"Functional programming","score":0.10423371195793152}],"concepts":[{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.9727077484130859},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.836438775062561},{"id":"https://openalex.org/C160191386","wikidata":"https://www.wikidata.org/wiki/Q868299","display_name":"Control flow","level":2,"score":0.6157482862472534},{"id":"https://openalex.org/C88468194","wikidata":"https://www.wikidata.org/wiki/Q1172416","display_name":"Data-flow analysis","level":3,"score":0.5878005027770996},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.5526161193847656},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.5409953594207764},{"id":"https://openalex.org/C489000","wikidata":"https://www.wikidata.org/wiki/Q747385","display_name":"Data flow diagram","level":2,"score":0.5305379033088684},{"id":"https://openalex.org/C173801870","wikidata":"https://www.wikidata.org/wiki/Q201413","display_name":"Heuristic","level":2,"score":0.5059186816215515},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.48545652627944946},{"id":"https://openalex.org/C188198153","wikidata":"https://www.wikidata.org/wiki/Q1613840","display_name":"Limiting","level":2,"score":0.46815255284309387},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.4599233567714691},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.45569270849227905},{"id":"https://openalex.org/C27458966","wikidata":"https://www.wikidata.org/wiki/Q1187693","display_name":"Control flow graph","level":2,"score":0.4540678858757019},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.45180052518844604},{"id":"https://openalex.org/C97042676","wikidata":"https://www.wikidata.org/wiki/Q5597097","display_name":"Graph reduction","level":3,"score":0.4300358295440674},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3480353057384491},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3448742628097534},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.32682955265045166},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2025536298751831},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.10828804969787598},{"id":"https://openalex.org/C42383842","wikidata":"https://www.wikidata.org/wiki/Q193076","display_name":"Functional programming","level":2,"score":0.10423371195793152},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":5,"locations":[{"id":"doi:10.1109/dsd.2017.31","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2017.31","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 Euromicro Conference on Digital System Design (DSD)","raw_type":"proceedings-article"},{"id":"pmh:oai:pure.tue.nl:openaire_cris_publications/1c1e69a6-0caa-4806-95db-b73ae91b75ea","is_oa":false,"landing_page_url":"https://research.tue.nl/en/publications/1c1e69a6-0caa-4806-95db-b73ae91b75ea","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Popp, M, van Son, S & Moreira, O 2017, Automatic control flow generation for openVX graphs. in M Novotny, H Kubatova & A Skavhaug (eds), Proceedings - 20th Euromicro Conference on Digital System Design, DSD 2017., 8049786, Institute of Electrical and Electronics Engineers, Piscataway, pp. 198-204, 20th Euromicro Conference on Digital System Design (DSD 2017), Vienna, Austria, 30/08/17. https://doi.org/10.1109/DSD.2017.31","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:903316","is_oa":false,"landing_page_url":"http://library.tue.nl/csp/dare/LinkToRepository.csp?recordnumber=903316","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":null},{"id":"pmh:oai:library.tue.nl:903316","is_oa":false,"landing_page_url":"http://repository.tue.nl/903316","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":null},{"id":"pmh:tue:oai:pure.tue.nl:publications/1c1e69a6-0caa-4806-95db-b73ae91b75ea","is_oa":false,"landing_page_url":"https://research.tue.nl/nl/publications/1c1e69a6-0caa-4806-95db-b73ae91b75ea","pdf_url":null,"source":{"id":"https://openalex.org/S4306401843","display_name":"Data Archiving and Networked Services (DANS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1322597698","host_organization_name":"Royal Netherlands Academy of Arts and Sciences","host_organization_lineage":["https://openalex.org/I1322597698"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Proceedings - 20th Euromicro Conference on Digital System Design, DSD 2017, 198 - 204","raw_type":"info:eu-repo/semantics/conferencepaper"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.6000000238418579,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1523847271","https://openalex.org/W1910515323","https://openalex.org/W1982621883","https://openalex.org/W2029804882","https://openalex.org/W2067264828","https://openalex.org/W2069195425","https://openalex.org/W2079752131","https://openalex.org/W2087656024","https://openalex.org/W2091158003","https://openalex.org/W2120080222","https://openalex.org/W2143111385","https://openalex.org/W2157504696","https://openalex.org/W2257028583","https://openalex.org/W2264426648","https://openalex.org/W2272080766","https://openalex.org/W2277741634","https://openalex.org/W2444333404","https://openalex.org/W2530752533","https://openalex.org/W2543492912","https://openalex.org/W2551094162","https://openalex.org/W3147536173","https://openalex.org/W4230467361","https://openalex.org/W4238421456","https://openalex.org/W4256068510","https://openalex.org/W4300544635","https://openalex.org/W6682841777","https://openalex.org/W6695115881"],"related_works":["https://openalex.org/W2058218097","https://openalex.org/W1999711970","https://openalex.org/W2166895275","https://openalex.org/W2151163382","https://openalex.org/W2998775986","https://openalex.org/W2052485000","https://openalex.org/W2030063121","https://openalex.org/W1971022286","https://openalex.org/W1565879960","https://openalex.org/W2052664195"],"abstract_inverted_index":{"Heterogeneous":[0],"platforms":[1],"with":[2,100],"large":[3],"numbers":[4],"of":[5,17,34,114],"processing":[6,57],"elements":[7],"(PEs)":[8],"have":[9],"been":[10],"proposed":[11],"to":[12,29,41,47,78,89,96,116,121],"satisfy":[13],"the":[14,22,31,91],"computational":[15],"requirements":[16],"computer":[18],"vision":[19,71],"applications.":[20],"Limiting":[21],"incurred":[23],"communication":[24,43,53,119],"cost":[25],"here":[26],"is":[27,61,76],"key":[28],"meet":[30],"power":[32],"constraints":[33],"embedded":[35],"devices.We":[36],"present":[37],"a":[38,97,112],"new":[39],"heuristic":[40],"reduce":[42],"among":[44],"PEs":[45],"and":[46,54,85],"external":[48],"memory":[49,103],"by":[50],"aggregating":[51],"inter-process":[52],"pipelining":[55],"image":[56],"functions.":[58],"The":[59],"application":[60,92],"specified":[62],"as":[63],"an":[64,67],"OpenVX":[65,123],"graph,":[66],"industry":[68],"standard":[69],"for":[70],"applications,":[72],"though":[73],"our":[74,108],"method":[75],"applicable":[77],"dataflow":[79,84],"in":[80,118],"general.":[81],"We":[82,105],"use":[83],"graph-based":[86],"analysis":[87],"techniques":[88],"map":[90],"at":[93],"configuration":[94],"time":[95],"hardware":[98],"platform":[99],"strong":[101],"program":[102],"constraints.":[104],"show":[106],"that":[107],"approach":[109],"can":[110],"yield":[111],"reduction":[113],"up":[115],"53%":[117],"compared":[120],"other":[122],"implementations.":[124]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2026-08-21T09:56:20.448147","created_date":"2025-10-10T00:00:00"}