{"id":"https://openalex.org/W3148148608","doi":"https://doi.org/10.1109/dsd.2007.4341502","title":"MPSoC memory optimization for digital camera applications","display_name":"MPSoC memory optimization for digital camera applications","publication_year":2007,"publication_date":"2007-08-01","ids":{"openalex":"https://openalex.org/W3148148608","doi":"https://doi.org/10.1109/dsd.2007.4341502","mag":"3148148608"},"language":"en","primary_location":{"id":"doi:10.1109/dsd.2007.4341502","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2007.4341502","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026685316","display_name":"Youcef Bouchebaba","orcid":null},"institutions":[{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Y. Bouchebaba","raw_affiliation_strings":["STMicroelectronics, Italy"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Italy","institution_ids":["https://openalex.org/I4210154781"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019380489","display_name":"Bruno Lavigueur","orcid":null},"institutions":[{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"B. Lavigueur","raw_affiliation_strings":["STMicroelectronics, Italy"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Italy","institution_ids":["https://openalex.org/I4210154781"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075649430","display_name":"B. Girodias","orcid":null},"institutions":[{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"B. Girodias","raw_affiliation_strings":["Ecole Polytechnique de Montr\u00e8al, Canada"],"affiliations":[{"raw_affiliation_string":"Ecole Polytechnique de Montr\u00e8al, Canada","institution_ids":["https://openalex.org/I45683168"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022527556","display_name":"Gabriela Nicolescu","orcid":"https://orcid.org/0000-0002-5205-9931"},"institutions":[{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"G. Nicolescu","raw_affiliation_strings":["Ecole Polytechnique de Montr\u00e8al, Canada"],"affiliations":[{"raw_affiliation_string":"Ecole Polytechnique de Montr\u00e8al, Canada","institution_ids":["https://openalex.org/I45683168"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073518200","display_name":"Pierre Paulin","orcid":null},"institutions":[{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"P. G. Paulin","raw_affiliation_strings":["STMicroelectronics, Italy"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Italy","institution_ids":["https://openalex.org/I4210154781"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5026685316"],"corresponding_institution_ids":["https://openalex.org/I4210154781"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.42338473,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"424","last_page":"427"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8379855155944824},{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.7945187091827393},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5892077088356018},{"id":"https://openalex.org/keywords/loop-fusion","display_name":"Loop fusion","score":0.5609146356582642},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5547307729721069},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5101197361946106},{"id":"https://openalex.org/keywords/locality-of-reference","display_name":"Locality of reference","score":0.5088046193122864},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.45717623829841614},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.44526994228363037},{"id":"https://openalex.org/keywords/loop-fission","display_name":"Loop fission","score":0.44152674078941345},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.43935829401016235},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4163004159927368},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.411734402179718},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.41132259368896484},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.131591796875},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.12591108679771423}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8379855155944824},{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.7945187091827393},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5892077088356018},{"id":"https://openalex.org/C82653869","wikidata":"https://www.wikidata.org/wiki/Q6675821","display_name":"Loop fusion","level":3,"score":0.5609146356582642},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5547307729721069},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5101197361946106},{"id":"https://openalex.org/C27602214","wikidata":"https://www.wikidata.org/wiki/Q1868547","display_name":"Locality of reference","level":3,"score":0.5088046193122864},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.45717623829841614},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.44526994228363037},{"id":"https://openalex.org/C134718785","wikidata":"https://www.wikidata.org/wiki/Q6675821","display_name":"Loop fission","level":3,"score":0.44152674078941345},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43935829401016235},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4163004159927368},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.411734402179718},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.41132259368896484},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.131591796875},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.12591108679771423},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dsd.2007.4341502","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2007.4341502","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.6700000166893005,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1522139285","https://openalex.org/W1966708457","https://openalex.org/W1973122629","https://openalex.org/W1985161391","https://openalex.org/W2029479717","https://openalex.org/W2046164356","https://openalex.org/W2059564324","https://openalex.org/W2106111212","https://openalex.org/W2134290033","https://openalex.org/W2143627170","https://openalex.org/W2144324947","https://openalex.org/W2164095419","https://openalex.org/W4232919122","https://openalex.org/W6654636865","https://openalex.org/W6657925059"],"related_works":["https://openalex.org/W2340721088","https://openalex.org/W1596526459","https://openalex.org/W1545258949","https://openalex.org/W2465949633","https://openalex.org/W2108315152","https://openalex.org/W4238138329","https://openalex.org/W2124711255","https://openalex.org/W2244841219","https://openalex.org/W2105287631","https://openalex.org/W4229933864"],"abstract_inverted_index":{"Multiprocessor":[0],"system-on-a-chip":[1],"architectures":[2,44],"have":[3],"received":[4],"a":[5,82,103,141],"lot":[6],"of":[7,30,34,60,79,147],"attention":[8],"in":[9,16,39,144,152,157],"the":[10,28,35,40,85,95,117,123,126,130,145],"past":[11],"years,":[12],"but":[13],"few":[14],"advances":[15],"compilation":[17,36],"techniques":[18,37,68],"are":[19,45,58,73],"targeting":[20],"these":[21,77],"architectures.":[22],"This":[23],"is":[24,89,98,112],"particularly":[25],"true":[26],"for":[27,42],"exploitation":[29],"data":[31,148],"locality.":[32],"Most":[33],"discussed":[38],"literature":[41],"parallel":[43],"based":[46,69],"on":[47,70],"single":[48],"loop":[49,62,86,96],"nest.":[50],"However,":[51],"most":[52],"multimedia":[53],"and":[54,100,120,129,156],"image":[55],"processing":[56,131,153],"applications":[57],"composed":[59],"several":[61],"nests.":[63],"In":[64,81,92],"this":[65,93,137],"paper,":[66,94],"new":[67,138],"program":[71],"transformations":[72],"proposed":[74],"to":[75,102],"optimize":[76],"types":[78],"applications.":[80],"monoprocessor":[83],"architecture,":[84],"fusion":[87,97],"technique":[88,107,139],"well":[90],"known.":[91],"generalized":[99],"adapted":[101],"MPSoC":[104],"architecture.":[105],"Another":[106],"called":[108],"\"computation":[109],"propagation":[110],"\"":[111],"proposed.":[113],"It":[114],"completely":[115],"removes":[116],"temporary":[118],"arrays":[119],"significantly":[121],"reduces":[122],"memory":[124,127],"accesses,":[125],"space":[128],"time.":[132],"Experimental":[133],"results":[134],"show":[135],"that":[136],"yields":[140],"significant":[142],"reduction":[143],"number":[146],"cache":[149],"misses":[150],"(35%),":[151],"time":[154],"(30%)":[155],"channel":[158],"transactions":[159],"(85%).":[160]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}