{"id":"https://openalex.org/W3146817988","doi":"https://doi.org/10.1109/dsd.2007.4341456","title":"An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector","display_name":"An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector","publication_year":2007,"publication_date":"2007-08-01","ids":{"openalex":"https://openalex.org/W3146817988","doi":"https://doi.org/10.1109/dsd.2007.4341456","mag":"3146817988"},"language":"en","primary_location":{"id":"doi:10.1109/dsd.2007.4341456","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2007.4341456","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5086085707","display_name":"Emanuele Sciagura","orcid":null},"institutions":[{"id":"https://openalex.org/I45204951","display_name":"University of Calabria","ror":"https://ror.org/02rc97e94","country_code":"IT","type":"education","lineage":["https://openalex.org/I45204951"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Emanuele Sciagura","raw_affiliation_strings":["University of Calabria-DEIS, Arcavacata di Rende, Italy"],"affiliations":[{"raw_affiliation_string":"University of Calabria-DEIS, Arcavacata di Rende, Italy","institution_ids":["https://openalex.org/I45204951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004014214","display_name":"Paolo Zicari","orcid":"https://orcid.org/0000-0002-9119-9865"},"institutions":[{"id":"https://openalex.org/I45204951","display_name":"University of Calabria","ror":"https://ror.org/02rc97e94","country_code":"IT","type":"education","lineage":["https://openalex.org/I45204951"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Paolo Zicari","raw_affiliation_strings":["University of Calabria-DEIS, Arcavacata di Rende, Italy"],"affiliations":[{"raw_affiliation_string":"University of Calabria-DEIS, Arcavacata di Rende, Italy","institution_ids":["https://openalex.org/I45204951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074662921","display_name":"Stefania Perri","orcid":"https://orcid.org/0000-0003-1363-9201"},"institutions":[{"id":"https://openalex.org/I45204951","display_name":"University of Calabria","ror":"https://ror.org/02rc97e94","country_code":"IT","type":"education","lineage":["https://openalex.org/I45204951"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Stefania Perri","raw_affiliation_strings":["University of Calabria-DEIS, Arcavacata di Rende, Italy"],"affiliations":[{"raw_affiliation_string":"University of Calabria-DEIS, Arcavacata di Rende, Italy","institution_ids":["https://openalex.org/I45204951"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5003003043","display_name":"Pasquale Corsonello","orcid":"https://orcid.org/0000-0002-9528-1110"},"institutions":[{"id":"https://openalex.org/I45204951","display_name":"University of Calabria","ror":"https://ror.org/02rc97e94","country_code":"IT","type":"education","lineage":["https://openalex.org/I45204951"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Pasquale Corsonello","raw_affiliation_strings":["University of Calabria-DEIS, Arcavacata di Rende, Italy"],"affiliations":[{"raw_affiliation_string":"University of Calabria-DEIS, Arcavacata di Rende, Italy","institution_ids":["https://openalex.org/I45204951"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5086085707"],"corresponding_institution_ids":["https://openalex.org/I45204951"],"apc_list":null,"apc_paid":null,"fwci":0.7025,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.76580728,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"102","last_page":"108"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10125","display_name":"Advanced Wireless Communication Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10125","display_name":"Advanced Wireless Communication Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10575","display_name":"Wireless Communication Networks Research","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8099160194396973},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6912826895713806},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.6823399662971497},{"id":"https://openalex.org/keywords/symbol","display_name":"Symbol (formal)","score":0.5533806085586548},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.5181676149368286},{"id":"https://openalex.org/keywords/symbol-rate","display_name":"Symbol rate","score":0.4922999143600464},{"id":"https://openalex.org/keywords/detector","display_name":"Detector","score":0.4720531105995178},{"id":"https://openalex.org/keywords/software-defined-radio","display_name":"Software-defined radio","score":0.4702405333518982},{"id":"https://openalex.org/keywords/matlab","display_name":"MATLAB","score":0.4537641108036041},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.43416187167167664},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.41426071524620056},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37292397022247314},{"id":"https://openalex.org/keywords/bit-error-rate","display_name":"Bit error rate","score":0.3033318519592285},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.18207785487174988},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08206680417060852}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8099160194396973},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6912826895713806},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.6823399662971497},{"id":"https://openalex.org/C134400042","wikidata":"https://www.wikidata.org/wiki/Q2372244","display_name":"Symbol (formal)","level":2,"score":0.5533806085586548},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.5181676149368286},{"id":"https://openalex.org/C74645175","wikidata":"https://www.wikidata.org/wiki/Q428083","display_name":"Symbol rate","level":4,"score":0.4922999143600464},{"id":"https://openalex.org/C94915269","wikidata":"https://www.wikidata.org/wiki/Q1834857","display_name":"Detector","level":2,"score":0.4720531105995178},{"id":"https://openalex.org/C171115542","wikidata":"https://www.wikidata.org/wiki/Q1331892","display_name":"Software-defined radio","level":2,"score":0.4702405333518982},{"id":"https://openalex.org/C2780365114","wikidata":"https://www.wikidata.org/wiki/Q169478","display_name":"MATLAB","level":2,"score":0.4537641108036041},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.43416187167167664},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.41426071524620056},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37292397022247314},{"id":"https://openalex.org/C56296756","wikidata":"https://www.wikidata.org/wiki/Q840922","display_name":"Bit error rate","level":3,"score":0.3033318519592285},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.18207785487174988},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08206680417060852},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dsd.2007.4341456","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2007.4341456","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1971114551","https://openalex.org/W2099611565","https://openalex.org/W2116930897","https://openalex.org/W2128028900","https://openalex.org/W2156272497","https://openalex.org/W2160574074","https://openalex.org/W2163937510","https://openalex.org/W2543359478","https://openalex.org/W4243959868","https://openalex.org/W6677325211","https://openalex.org/W6728705191","https://openalex.org/W7018733341"],"related_works":["https://openalex.org/W1576949837","https://openalex.org/W2097523295","https://openalex.org/W4360861688","https://openalex.org/W3134930219","https://openalex.org/W984417604","https://openalex.org/W2967785526","https://openalex.org/W2908000842","https://openalex.org/W2148499256","https://openalex.org/W2548863666","https://openalex.org/W2013462106"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3],"efficient":[4],"and":[5,27,76],"optimized":[6],"FPGA":[7,62],"implementation":[8],"of":[9,81,87],"a":[10,20,29,57,78,84],"complete":[11,30],"digital":[12,21],"Symbol":[13],"Timing":[14],"Recovery":[15],"(STR)":[16],"architecture":[17],"based":[18],"on":[19,56],"PLL":[22],"loop":[23],"structure.":[24],"Matlab":[25],"modelling":[26],"then":[28],"hardware":[31],"communication":[32],"system":[33,112],"test,":[34],"reveal":[35],"that":[36],"the":[37,42,47,64],"implemented":[38,49,55],"STR":[39,66],"circuit":[40,67],"offers":[41],"best":[43],"performances":[44],"compared":[45],"with":[46],"other":[48],"works":[50],"present":[51],"in":[52,108],"literature.":[53],"When":[54],"Xilinx":[58],"Virtex-2P":[59],"XC2VP7":[60],"FF672":[61],"chip":[63],"proposed":[65],"occupies":[68],"just":[69],"138":[70],"slices,":[71],"uses":[72],"2":[73],"embedded":[74],"multipliers":[75],"reaches":[77],"clock":[79],"frequency":[80],"106":[82],"MHz;":[83],"symbol":[85,97],"rate":[86],"10":[88,94],"Msymbol/sec":[89],"can":[90],"be":[91],"reached":[92],"when":[93],"samples":[95],"per":[96],"are":[98,103],"employed.":[99],"The":[100],"obtained":[101],"results":[102],"promising":[104],"for":[105],"its":[106],"use":[107],"software":[109],"defined":[110],"radio":[111],"applications.":[113]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}