{"id":"https://openalex.org/W2102001548","doi":"https://doi.org/10.1109/dftvs.2002.1173523","title":"Fault list compaction through static timing analysis for efficient fault injection experiments","display_name":"Fault list compaction through static timing analysis for efficient fault injection experiments","publication_year":2003,"publication_date":"2003-06-26","ids":{"openalex":"https://openalex.org/W2102001548","doi":"https://doi.org/10.1109/dftvs.2002.1173523","mag":"2102001548"},"language":"en","primary_location":{"id":"doi:10.1109/dftvs.2002.1173523","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dftvs.2002.1173523","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5058555274","display_name":"M. Sonza Reorda","orcid":"https://orcid.org/0000-0003-2899-7669"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"M.S. Reorda","raw_affiliation_strings":["Politecnico di Torino, Torino, Italy","Politecnico di Torino, (Italy)"],"affiliations":[{"raw_affiliation_string":"Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Politecnico di Torino, (Italy)","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5087219426","display_name":"M. Violante","orcid":"https://orcid.org/0000-0002-5821-3418"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Violante","raw_affiliation_strings":["Politecnico di Torino, Torino, Italy","Politecnico di Torino, (Italy)"],"affiliations":[{"raw_affiliation_string":"Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Politecnico di Torino, (Italy)","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5058555274"],"corresponding_institution_ids":["https://openalex.org/I177477856"],"apc_list":null,"apc_paid":null,"fwci":2.434,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.89053357,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"263","last_page":"271"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6795592308044434},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.6296369433403015},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.6042545437812805},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5781769752502441},{"id":"https://openalex.org/keywords/fault-injection","display_name":"Fault injection","score":0.5587801337242126},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.5561919808387756},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5308944582939148},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.501610517501831},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.466123104095459},{"id":"https://openalex.org/keywords/event","display_name":"Event (particle physics)","score":0.4471926987171173},{"id":"https://openalex.org/keywords/fault-model","display_name":"Fault model","score":0.42400503158569336},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.4097887873649597},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.39688533544540405},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.31131523847579956},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.2545078694820404},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2368677258491516},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.2240055799484253},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22158530354499817},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.09426289796829224},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.07971218228340149}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6795592308044434},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.6296369433403015},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.6042545437812805},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5781769752502441},{"id":"https://openalex.org/C2775928411","wikidata":"https://www.wikidata.org/wiki/Q2041312","display_name":"Fault injection","level":3,"score":0.5587801337242126},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.5561919808387756},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5308944582939148},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.501610517501831},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.466123104095459},{"id":"https://openalex.org/C2779662365","wikidata":"https://www.wikidata.org/wiki/Q5416694","display_name":"Event (particle physics)","level":2,"score":0.4471926987171173},{"id":"https://openalex.org/C167391956","wikidata":"https://www.wikidata.org/wiki/Q1401211","display_name":"Fault model","level":3,"score":0.42400503158569336},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4097887873649597},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.39688533544540405},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.31131523847579956},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.2545078694820404},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2368677258491516},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.2240055799484253},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22158530354499817},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.09426289796829224},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.07971218228340149},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dftvs.2002.1173523","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dftvs.2002.1173523","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1570316473","https://openalex.org/W1892111635","https://openalex.org/W1908654170","https://openalex.org/W2013185880","https://openalex.org/W2072194206","https://openalex.org/W2089244748","https://openalex.org/W2098513789","https://openalex.org/W2101309301","https://openalex.org/W2123651866","https://openalex.org/W2128200969","https://openalex.org/W2144371588","https://openalex.org/W2148602057","https://openalex.org/W2169352387","https://openalex.org/W4235799760","https://openalex.org/W6634231543","https://openalex.org/W6639821308"],"related_works":["https://openalex.org/W2075328278","https://openalex.org/W2051500795","https://openalex.org/W1600260729","https://openalex.org/W3216514701","https://openalex.org/W2120242933","https://openalex.org/W2130922779","https://openalex.org/W2742111403","https://openalex.org/W2185394135","https://openalex.org/W2082366402","https://openalex.org/W2083209667"],"abstract_inverted_index":{"With":[0],"the":[1,44,64,70,81,88,99,102],"adoption":[2],"of":[3,46,72,80,101],"deep":[4],"sub-micron":[5],"technologies,":[6],"faults":[7,47,74],"modeled":[8],"as":[9],"single":[10],"event":[11],"transients":[12],"(SETS)":[13],"on":[14,30,87,95],"combinational":[15],"gates":[16],"are":[17,33,93],"becoming":[18],"an":[19],"issue,":[20],"but":[21],"efficient":[22],"and":[23,75],"accurate":[24],"techniques":[25],"for":[26,42],"assessing":[27,98],"their":[28],"impact":[29],"VLSI":[31],"designs":[32],"still":[34],"missing.":[35],"This":[36],"paper":[37],"presents":[38],"a":[39,78],"new":[40],"approach":[41,65],"generating":[43],"list":[45],"to":[48,60,68,76],"be":[49],"addressed":[50],"during":[51],"fault":[52],"injection":[53],"experiments":[54],"tackling":[55],"SET":[56],"effects.":[57],"By":[58],"resorting":[59],"static":[61],"timing":[62],"analysis,":[63],"is":[66],"able":[67],"prune":[69],"set":[71],"possible":[73],"identify":[77],"superset":[79],"ones":[82],"that":[83],"may":[84],"produce":[85],"effects":[86],"circuit":[89],"outputs.":[90],"Experimental":[91],"results":[92],"reported":[94],"standard":[96],"benchmarks":[97],"effectiveness":[100],"proposed":[103],"approach.":[104]},"counts_by_year":[{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
