{"id":"https://openalex.org/W2011745694","doi":"https://doi.org/10.1109/dft.2014.6962090","title":"On the in-field functional testing of decode units in pipelined RISC processors","display_name":"On the in-field functional testing of decode units in pipelined RISC processors","publication_year":2014,"publication_date":"2014-10-01","ids":{"openalex":"https://openalex.org/W2011745694","doi":"https://doi.org/10.1109/dft.2014.6962090","mag":"2011745694"},"language":"en","primary_location":{"id":"doi:10.1109/dft.2014.6962090","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft.2014.6962090","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049430681","display_name":"Paolo Bernardi","orcid":"https://orcid.org/0000-0002-0985-9327"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"P. Bernardi","raw_affiliation_strings":["Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy","Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino,Italy#TAB#"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino,Italy#TAB#","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089672314","display_name":"Riccardo Cantoro","orcid":"https://orcid.org/0000-0002-1745-5293"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"R. Cantoro","raw_affiliation_strings":["Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy","Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino,Italy#TAB#"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino,Italy#TAB#","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067849496","display_name":"L. Ciganda","orcid":null},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"L. Ciganda","raw_affiliation_strings":["Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy","Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino,Italy#TAB#"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino,Italy#TAB#","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009336869","display_name":"Ernesto S\u00e1nchez","orcid":"https://orcid.org/0000-0002-7042-295X"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"E. Sanchez","raw_affiliation_strings":["Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy","Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino,Italy#TAB#"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino,Italy#TAB#","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058555274","display_name":"M. Sonza Reorda","orcid":"https://orcid.org/0000-0003-2899-7669"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Sonza Reorda","raw_affiliation_strings":["Politecnico di Torino, Torino, Piemonte, IT","Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino,Italy#TAB#"],"affiliations":[{"raw_affiliation_string":"Politecnico di Torino, Torino, Piemonte, IT","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino,Italy#TAB#","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":null,"display_name":"S. De Luca","orcid":null},"institutions":[{"id":"https://openalex.org/I131827901","display_name":"STMicroelectronics (Switzerland)","ror":"https://ror.org/00wm3b005","country_code":"CH","type":"company","lineage":["https://openalex.org/I131827901"]},{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["CH","IT"],"is_corresponding":false,"raw_author_name":"S. De Luca","raw_affiliation_strings":["STMicroelectronics, Agrate Brianza, Italy","STMicroelectronics - Agrate Brianza, Italy"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Agrate Brianza, Italy","institution_ids":["https://openalex.org/I4210154781"]},{"raw_affiliation_string":"STMicroelectronics - Agrate Brianza, Italy","institution_ids":["https://openalex.org/I131827901"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048728176","display_name":"R. Meregalli","orcid":null},"institutions":[{"id":"https://openalex.org/I131827901","display_name":"STMicroelectronics (Switzerland)","ror":"https://ror.org/00wm3b005","country_code":"CH","type":"company","lineage":["https://openalex.org/I131827901"]},{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["CH","IT"],"is_corresponding":false,"raw_author_name":"R. Meregalli","raw_affiliation_strings":["STMicroelectronics, Agrate Brianza, Italy","STMicroelectronics - Agrate Brianza, Italy"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Agrate Brianza, Italy","institution_ids":["https://openalex.org/I4210154781"]},{"raw_affiliation_string":"STMicroelectronics - Agrate Brianza, Italy","institution_ids":["https://openalex.org/I131827901"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039083378","display_name":"A. Sansonetti","orcid":null},"institutions":[{"id":"https://openalex.org/I131827901","display_name":"STMicroelectronics (Switzerland)","ror":"https://ror.org/00wm3b005","country_code":"CH","type":"company","lineage":["https://openalex.org/I131827901"]},{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["CH","IT"],"is_corresponding":false,"raw_author_name":"A. Sansonetti","raw_affiliation_strings":["STMicroelectronics, Agrate Brianza, Italy","STMicroelectronics - Agrate Brianza, Italy"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Agrate Brianza, Italy","institution_ids":["https://openalex.org/I4210154781"]},{"raw_affiliation_string":"STMicroelectronics - Agrate Brianza, Italy","institution_ids":["https://openalex.org/I131827901"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5049430681"],"corresponding_institution_ids":["https://openalex.org/I177477856"],"apc_list":null,"apc_paid":null,"fwci":2.5204,"has_fulltext":false,"cited_by_count":21,"citation_normalized_percentile":{"value":0.89054642,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"299","last_page":"304"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7456997632980347},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.6301631927490234},{"id":"https://openalex.org/keywords/field","display_name":"Field (mathematics)","score":0.5836606621742249},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5142919421195984},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4119792580604553},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3654104769229889},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.31466907262802124}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7456997632980347},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.6301631927490234},{"id":"https://openalex.org/C9652623","wikidata":"https://www.wikidata.org/wiki/Q190109","display_name":"Field (mathematics)","level":2,"score":0.5836606621742249},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5142919421195984},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4119792580604553},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3654104769229889},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.31466907262802124},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/dft.2014.6962090","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft.2014.6962090","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","raw_type":"proceedings-article"},{"id":"pmh:oai:porto.polito.it:2570736","is_oa":false,"landing_page_url":"http://porto.polito.it/2570736/","pdf_url":null,"source":{"id":"https://openalex.org/S4306402038","display_name":"PORTO Publications Open Repository TOrino (Politecnico di Torino)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I177477856","host_organization_name":"Politecnico di Torino","host_organization_lineage":["https://openalex.org/I177477856"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1555915743","https://openalex.org/W1823755974","https://openalex.org/W1965015817","https://openalex.org/W1968989269","https://openalex.org/W2066121188","https://openalex.org/W2137743612","https://openalex.org/W2162696040","https://openalex.org/W2168140292","https://openalex.org/W2548414015"],"related_works":["https://openalex.org/W2538644970","https://openalex.org/W4376881175","https://openalex.org/W4310584696","https://openalex.org/W4385730960","https://openalex.org/W4237840813","https://openalex.org/W4364295250","https://openalex.org/W2128502296","https://openalex.org/W1998013902","https://openalex.org/W2993622674","https://openalex.org/W1833044483"],"abstract_inverted_index":{"The":[0,24,38,62],"paper":[1,25],"is":[2,53,65],"dealing":[3],"with":[4],"the":[5,9,21,43,50,56,60,80,85,87],"in-field":[6],"test":[7,18],"of":[8,12,45,59,84,93],"decode":[10],"unit":[11],"RIS":[13],"C":[14],"processors":[15],"through":[16],"functional":[17],"programs":[19],"following":[20],"SBST":[22],"approach.":[23],"details":[26],"a":[27,74],"strategy":[28],"based":[29,54,101],"on":[30,55,67],"instruction":[31,99],"classification":[32],"and":[33,35,82],"manipulation,":[34],"signatures":[36],"collection.":[37],"method":[39,64],"does":[40,103],"not":[41,104],"require":[42],"knowledge":[44],"detailed":[46],"implementation":[47],"information":[48],"(e.g.,":[49],"netlist),":[51],"but":[52],"Instruction":[57],"Set":[58],"processor.":[61,77],"proposed":[63,88],"evaluated":[66],"an":[68,98],"industrial":[69],"SoC":[70],"device,":[71],"which":[72],"includes":[73],"PowerPC":[75],"derived":[76],"Results":[78],"demonstrate":[79],"efficiency":[81],"effectiveness":[83],"strategy;":[86],"solution":[89],"reaches":[90],"over":[91],"90%":[92],"stuck-at":[94],"fault":[95],"coverage":[96,100],"while":[97],"approach":[102],"overcome":[105],"70%.":[106]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":3}],"updated_date":"2026-04-16T08:26:57.006410","created_date":"2025-10-10T00:00:00"}
