{"id":"https://openalex.org/W1967105255","doi":"https://doi.org/10.1109/dft.2012.6378204","title":"Single event upset tolerance in flip-flop based microprocessor cores","display_name":"Single event upset tolerance in flip-flop based microprocessor cores","publication_year":2012,"publication_date":"2012-10-01","ids":{"openalex":"https://openalex.org/W1967105255","doi":"https://doi.org/10.1109/dft.2012.6378204","mag":"1967105255"},"language":"en","primary_location":{"id":"doi:10.1109/dft.2012.6378204","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft.2012.6378204","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5052066445","display_name":"Stefanos Valadimas","orcid":null},"institutions":[{"id":"https://openalex.org/I200777214","display_name":"National and Kapodistrian University of Athens","ror":"https://ror.org/04gnjpq42","country_code":"GR","type":"education","lineage":["https://openalex.org/I200777214"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"Stefanos Valadimas","raw_affiliation_strings":["Department of Informatics and Telecommunications, University of Athens (NKUA), Athens, Greece"],"affiliations":[{"raw_affiliation_string":"Department of Informatics and Telecommunications, University of Athens (NKUA), Athens, Greece","institution_ids":["https://openalex.org/I200777214"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036684985","display_name":"Yiorgos Tsiatouhas","orcid":"https://orcid.org/0000-0001-8408-6929"},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I194019607","display_name":"University of Ioannina","ror":"https://ror.org/01qg3j183","country_code":"GR","type":"education","lineage":["https://openalex.org/I194019607"]}],"countries":["FR","GR"],"is_corresponding":false,"raw_author_name":"Yiorgos Tsiatouhas","raw_affiliation_strings":["Department of Computer Science, University of Ioannina (UoI), Ioannina, Greece","TIMA Laboratory, CNRS, Grenoble, France"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Ioannina (UoI), Ioannina, Greece","institution_ids":["https://openalex.org/I194019607"]},{"raw_affiliation_string":"TIMA Laboratory, CNRS, Grenoble, France","institution_ids":["https://openalex.org/I4210087012","https://openalex.org/I1294671590"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113664438","display_name":"Angela Arapoyanni","orcid":null},"institutions":[{"id":"https://openalex.org/I200777214","display_name":"National and Kapodistrian University of Athens","ror":"https://ror.org/04gnjpq42","country_code":"GR","type":"education","lineage":["https://openalex.org/I200777214"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Angela Arapoyanni","raw_affiliation_strings":["Department of Informatics and Telecommunications, University of Athens (NKUA), Athens, Greece"],"affiliations":[{"raw_affiliation_string":"Department of Informatics and Telecommunications, University of Athens (NKUA), Athens, Greece","institution_ids":["https://openalex.org/I200777214"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028414036","display_name":"Adrian Evans","orcid":"https://orcid.org/0000-0002-2617-5007"},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Adrian Evans","raw_affiliation_strings":["TIMA Laboratory, CNRS, Grenoble, France"],"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, CNRS, Grenoble, France","institution_ids":["https://openalex.org/I4210087012","https://openalex.org/I1294671590"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5052066445"],"corresponding_institution_ids":["https://openalex.org/I200777214"],"apc_list":null,"apc_paid":null,"fwci":0.2492,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.56706294,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"79","last_page":"84"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.995199978351593,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/soft-error","display_name":"Soft error","score":0.8720824718475342},{"id":"https://openalex.org/keywords/flip-flop","display_name":"Flip-flop","score":0.8223403692245483},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.7455668449401855},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6839731931686401},{"id":"https://openalex.org/keywords/single-event-upset","display_name":"Single event upset","score":0.6812222599983215},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.6411430835723877},{"id":"https://openalex.org/keywords/flops","display_name":"FLOPS","score":0.6344517469406128},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.5144994258880615},{"id":"https://openalex.org/keywords/detector","display_name":"Detector","score":0.5094080567359924},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5043421983718872},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4595455527305603},{"id":"https://openalex.org/keywords/upset","display_name":"Upset","score":0.45459723472595215},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4060969948768616},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3682173490524292},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3335719108581543},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.28839313983917236},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.19517996907234192},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1780572235584259},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.11256149411201477},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10780608654022217}],"concepts":[{"id":"https://openalex.org/C154474529","wikidata":"https://www.wikidata.org/wiki/Q1658917","display_name":"Soft error","level":2,"score":0.8720824718475342},{"id":"https://openalex.org/C2781007278","wikidata":"https://www.wikidata.org/wiki/Q183406","display_name":"Flip-flop","level":3,"score":0.8223403692245483},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.7455668449401855},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6839731931686401},{"id":"https://openalex.org/C2780073065","wikidata":"https://www.wikidata.org/wiki/Q1476733","display_name":"Single event upset","level":3,"score":0.6812222599983215},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.6411430835723877},{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.6344517469406128},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.5144994258880615},{"id":"https://openalex.org/C94915269","wikidata":"https://www.wikidata.org/wiki/Q1834857","display_name":"Detector","level":2,"score":0.5094080567359924},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5043421983718872},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4595455527305603},{"id":"https://openalex.org/C2778002589","wikidata":"https://www.wikidata.org/wiki/Q2406791","display_name":"Upset","level":2,"score":0.45459723472595215},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4060969948768616},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3682173490524292},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3335719108581543},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.28839313983917236},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.19517996907234192},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1780572235584259},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.11256149411201477},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10780608654022217},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/dft.2012.6378204","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft.2012.6378204","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-01061344v1","is_oa":false,"landing_page_url":"https://hal.science/hal-01061344","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2012, Austin, Texas, United States. pp.79 - 84, &#x27E8;10.1109/DFT.2012.6378204&#x27E9;","raw_type":"Conference papers"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1541483005","https://openalex.org/W1906369229","https://openalex.org/W1999298172","https://openalex.org/W2001611266","https://openalex.org/W2003060778","https://openalex.org/W2013185880","https://openalex.org/W2015917466","https://openalex.org/W2051973459","https://openalex.org/W2060193918","https://openalex.org/W2104677471","https://openalex.org/W2106648230","https://openalex.org/W2138634741","https://openalex.org/W2149051075","https://openalex.org/W2151802820","https://openalex.org/W2156667996","https://openalex.org/W2161033118","https://openalex.org/W2162465831","https://openalex.org/W2163094833","https://openalex.org/W2178304595","https://openalex.org/W4229966209","https://openalex.org/W4236432903","https://openalex.org/W4299639710"],"related_works":["https://openalex.org/W2102538861","https://openalex.org/W1523508240","https://openalex.org/W2622269177","https://openalex.org/W2086616086","https://openalex.org/W2978528242","https://openalex.org/W2165400042","https://openalex.org/W2130033702","https://openalex.org/W2160088500","https://openalex.org/W3208260600","https://openalex.org/W2081303028"],"abstract_inverted_index":{"Soft":[0],"errors":[1],"due":[2],"to":[3,59],"single":[4],"event":[5],"upsets":[6],"(SEUs)":[7],"in":[8,18,98],"the":[9,43,46,91,99],"flip-flops":[10],"of":[11,15,45,101],"a":[12,28,39,65,76,102,108],"design":[13,100],"are":[14],"increasing":[16],"importance":[17],"nanometer":[19],"technology":[20],"microprocessor":[21,105],"cores.":[22],"In":[23],"this":[24],"work,":[25],"we":[26],"present":[27],"flip-flop":[29,47],"oriented":[30],"soft":[31,61,68],"error":[32,49,56,62,69,83],"detection":[33,50,70],"and":[34],"correction":[35,57],"technique.":[36],"It":[37],"exploits":[38],"transition":[40,77],"detector":[41,78],"at":[42],"output":[44],"for":[48],"along":[51],"with":[52],"an":[53],"asynchronous":[54],"local":[55],"scheme":[58,71],"provide":[60],"tolerance.":[63],"Alternatively,":[64],"low":[66],"cost":[67],"is":[72],"introduced,":[73],"which":[74],"shares":[75],"among":[79],"multiple":[80],"flip-flops,":[81],"while":[82],"recovery":[84],"relies":[85],"on":[86],"architectural":[87],"replay.":[88],"To":[89],"validate":[90],"proposed":[92],"approach,":[93],"it":[94],"has":[95],"been":[96],"applied":[97],"32-bit":[103],"MIPS":[104],"core":[106],"using":[107],"90nm":[109],"CMOS":[110],"technology.":[111]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-03-10T16:38:18.471706","created_date":"2025-10-10T00:00:00"}
