{"id":"https://openalex.org/W1968950054","doi":"https://doi.org/10.1109/dft.2009.65","title":"A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap CMOS","display_name":"A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap CMOS","publication_year":2009,"publication_date":"2009-10-01","ids":{"openalex":"https://openalex.org/W1968950054","doi":"https://doi.org/10.1109/dft.2009.65","mag":"1968950054"},"language":"en","primary_location":{"id":"doi:10.1109/dft.2009.65","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft.2009.65","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5104362993","display_name":"Adit D. Singh","orcid":null},"institutions":[{"id":"https://openalex.org/I82497590","display_name":"Auburn University","ror":"https://ror.org/02v80fc35","country_code":"US","type":"education","lineage":["https://openalex.org/I82497590"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Adit D. Singh","raw_affiliation_strings":["Electrical & Computer Engineering, Aubum University, AL, USA","Electr. & Comput. Eng., Auburn Univ., Auburn, AL, USA"],"affiliations":[{"raw_affiliation_string":"Electrical & Computer Engineering, Aubum University, AL, USA","institution_ids":[]},{"raw_affiliation_string":"Electr. & Comput. Eng., Auburn Univ., Auburn, AL, USA","institution_ids":["https://openalex.org/I82497590"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5104362993"],"corresponding_institution_ids":["https://openalex.org/I82497590"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.05652531,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"422","last_page":"422"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9944999814033508,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7604467272758484},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.6714329123497009},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5856376886367798},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.5760536193847656},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5215415954589844},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5095162987709045},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.4569947123527527},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4454723000526428},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4409271776676178},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3697465658187866},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.30785036087036133},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.12156155705451965},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.11046171188354492}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7604467272758484},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.6714329123497009},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5856376886367798},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.5760536193847656},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5215415954589844},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5095162987709045},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.4569947123527527},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4454723000526428},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4409271776676178},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3697465658187866},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.30785036087036133},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.12156155705451965},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.11046171188354492}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dft.2009.65","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft.2009.65","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2730314563","https://openalex.org/W4400386354","https://openalex.org/W2058541779","https://openalex.org/W2120538654","https://openalex.org/W1632369502","https://openalex.org/W2971786152","https://openalex.org/W1997318576","https://openalex.org/W3129152221","https://openalex.org/W2135286216","https://openalex.org/W2170979950"],"abstract_inverted_index":{"Summary":[0],"form":[1],"only":[2,206],"given.":[3],"In":[4,117],"addition":[5],"to":[6,20,32,55,68,157,179],"high":[7],"defect":[8,149,166,273],"rates,":[9],"end-of-roadmap":[10],"CMOS":[11,127,147,152,220],"at":[12,253],"sub-10":[13],"nm":[14],"gate":[15,129,154,160,192,252],"lengths":[16],"is":[17,51,76,155],"also":[18,94,223,236],"expected":[19],"display":[21],"significant":[22,72],"random":[23],"variability":[24],"in":[25,41,86,145,161,197,217,262],"individual":[26,42,111],"device":[27],"performance.":[28],"This":[29],"will":[30,66,93],"lead":[31],"unique":[33],"and":[34,60,204,275],"varied":[35],"slow":[36,108,247,260],"paths":[37,109],"(statistical":[38],"performance":[39,82,99,242,276],"outliers)":[40],"ICs,":[43],"severely":[44],"limiting":[45],"achievable":[46],"clock":[47,115],"rates.":[48,116],"While":[49],"it":[50,75],"widely":[52],"accepted":[53],"that":[54,80,113],"ensure":[56],"viable":[57],"manufacturing":[58],"yield":[59],"reliable":[61],"field":[62],"operation,":[63],"future":[64],"circuits":[65],"need":[67],"be":[69,224,237],"equipped":[70],"with":[71],"defect-tolerance":[73],"capabilities,":[74],"less":[77],"commonly":[78],"recognized":[79],"continued":[81],"gains":[83],"from":[84],"scaling":[85],"the":[87,106,141,151,162,181,189,199,214,254,263,268,271],"face":[88],"of":[89,103,164,257,270],"extreme":[90],"parameter":[91],"variations":[92],"require":[95],"a":[96,123,158,165,207,218,246,251,258],"post":[97],"manufacture":[98],"tuning":[100,277],"capability":[101],"capable":[102],"speeding":[104,244],"up":[105,174,230,245],"statistical":[107],"on":[110,240],"ICs":[112],"limit":[114],"this":[118],"paper,":[119],"we":[120],"show":[121],"how":[122],"recently":[124],"proposed":[125],"defect-tolerant":[126,191],"logic":[128,153,215],"architecture":[130,193],"can":[131,194,222,235],"efficiently":[132],"achieve":[133],"both":[134],"these":[135,227],"goals.":[136],"Our":[137],"basic":[138],"design":[139,221],"exploits":[140],"inherent":[142],"functional":[143],"redundancy":[144],"static":[146],"for":[148,241],"tolerance;":[150],"reconfigured":[156],"pseudo-NMOS-like":[159],"presence":[163],"by":[167],"using":[168],"an":[169],"appropriately":[170],"sized":[171],"single":[172],"pull":[173,176,185,229,232],"or":[175,184,201,231],"down":[177,186,233,261],"transistor":[178],"replace":[180],"defective":[182],"pull-up":[183,200],"network.":[187],"Thus":[188],"resulting":[190],"tolerate":[195],"defects":[196,212],"either":[198],"pull-down":[202],"network":[203],"incurs":[205],"modest":[208],"area":[209],"overhead.":[210],"Multiple":[211],"across":[213],"gates":[216],"large":[219],"tolerated.":[225],"Importantly,":[226],"redundant":[228],"transistors":[234],"strategically":[238],"turned":[239],"tuning,":[243],"critical":[248],"transition":[249],"through":[250],"possible":[255],"expense":[256],"small":[259],"opposite":[264],"transition.":[265],"Results":[266],"evaluating":[267],"effectiveness":[269],"new":[272],"tolerance":[274],"technique":[278],"are":[279],"presented.":[280]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}