{"id":"https://openalex.org/W3028027935","doi":"https://doi.org/10.1109/ddecs50862.2020.9095658","title":"Sensitivity Analysis and Compression Opportunities in DNNs Using Weight Sharing","display_name":"Sensitivity Analysis and Compression Opportunities in DNNs Using Weight Sharing","publication_year":2020,"publication_date":"2020-04-01","ids":{"openalex":"https://openalex.org/W3028027935","doi":"https://doi.org/10.1109/ddecs50862.2020.9095658","mag":"3028027935"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs50862.2020.9095658","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs50862.2020.9095658","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://hal-lirmm.ccsd.cnrs.fr/lirmm-03054134","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112641892","display_name":"Etienne Dupuis","orcid":null},"institutions":[{"id":"https://openalex.org/I112936343","display_name":"\u00c9cole Centrale de Lyon","ror":"https://ror.org/05s6rge65","country_code":"FR","type":"education","lineage":["https://openalex.org/I112936343","https://openalex.org/I203339264"]},{"id":"https://openalex.org/I2800958632","display_name":"Institut des Nanotechnologies de Lyon","ror":"https://ror.org/04jsk0b74","country_code":"FR","type":"facility","lineage":["https://openalex.org/I100532134","https://openalex.org/I112936343","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I203339264","https://openalex.org/I203339264","https://openalex.org/I203339264","https://openalex.org/I2800958632","https://openalex.org/I4210095849","https://openalex.org/I48430043","https://openalex.org/I59692284"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Etienne Dupuis","raw_affiliation_strings":["Ecole Centrale de Lyon, Institut des Nanotechnologies de Lyon, France"],"affiliations":[{"raw_affiliation_string":"Ecole Centrale de Lyon, Institut des Nanotechnologies de Lyon, France","institution_ids":["https://openalex.org/I2800958632","https://openalex.org/I112936343"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102760981","display_name":"David Novo","orcid":"https://orcid.org/0000-0002-5510-4152"},"institutions":[{"id":"https://openalex.org/I4210101743","display_name":"Laboratoire d'Informatique, de Robotique et de Micro\u00e9lectronique de Montpellier","ror":"https://ror.org/013yean28","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I151295451","https://openalex.org/I19894307","https://openalex.org/I4210101743","https://openalex.org/I4210159245","https://openalex.org/I4405261681"]},{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I19894307","display_name":"Universit\u00e9 de Montpellier","ror":"https://ror.org/051escj72","country_code":"FR","type":"education","lineage":["https://openalex.org/I19894307"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"David Novo","raw_affiliation_strings":["LIRMM, Universit\u00e9 de Montpellier, CNRS, France"],"affiliations":[{"raw_affiliation_string":"LIRMM, Universit\u00e9 de Montpellier, CNRS, France","institution_ids":["https://openalex.org/I19894307","https://openalex.org/I4210101743","https://openalex.org/I1294671590"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057554410","display_name":"Ian O\u2019Connor","orcid":"https://orcid.org/0000-0002-6238-9600"},"institutions":[{"id":"https://openalex.org/I112936343","display_name":"\u00c9cole Centrale de Lyon","ror":"https://ror.org/05s6rge65","country_code":"FR","type":"education","lineage":["https://openalex.org/I112936343","https://openalex.org/I203339264"]},{"id":"https://openalex.org/I2800958632","display_name":"Institut des Nanotechnologies de Lyon","ror":"https://ror.org/04jsk0b74","country_code":"FR","type":"facility","lineage":["https://openalex.org/I100532134","https://openalex.org/I112936343","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I203339264","https://openalex.org/I203339264","https://openalex.org/I203339264","https://openalex.org/I2800958632","https://openalex.org/I4210095849","https://openalex.org/I48430043","https://openalex.org/I59692284"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Ian O'Connor","raw_affiliation_strings":["Ecole Centrale de Lyon, Institut des Nanotechnologies de Lyon, France"],"affiliations":[{"raw_affiliation_string":"Ecole Centrale de Lyon, Institut des Nanotechnologies de Lyon, France","institution_ids":["https://openalex.org/I2800958632","https://openalex.org/I112936343"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074986688","display_name":"Alberto Bosio","orcid":"https://orcid.org/0000-0001-6116-7339"},"institutions":[{"id":"https://openalex.org/I112936343","display_name":"\u00c9cole Centrale de Lyon","ror":"https://ror.org/05s6rge65","country_code":"FR","type":"education","lineage":["https://openalex.org/I112936343","https://openalex.org/I203339264"]},{"id":"https://openalex.org/I2800958632","display_name":"Institut des Nanotechnologies de Lyon","ror":"https://ror.org/04jsk0b74","country_code":"FR","type":"facility","lineage":["https://openalex.org/I100532134","https://openalex.org/I112936343","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I203339264","https://openalex.org/I203339264","https://openalex.org/I203339264","https://openalex.org/I2800958632","https://openalex.org/I4210095849","https://openalex.org/I48430043","https://openalex.org/I59692284"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Alberto Bosio","raw_affiliation_strings":["Ecole Centrale de Lyon, Institut des Nanotechnologies de Lyon, France"],"affiliations":[{"raw_affiliation_string":"Ecole Centrale de Lyon, Institut des Nanotechnologies de Lyon, France","institution_ids":["https://openalex.org/I2800958632","https://openalex.org/I112936343"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5112641892"],"corresponding_institution_ids":["https://openalex.org/I112936343","https://openalex.org/I2800958632"],"apc_list":null,"apc_paid":null,"fwci":1.1302,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.77616051,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9958999752998352,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7117018103599548},{"id":"https://openalex.org/keywords/sensitivity","display_name":"Sensitivity (control systems)","score":0.6321938633918762},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.5277329683303833},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4650629162788391},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4539225101470947},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.43053171038627625},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.4105827212333679},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4067310392856598},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.30080634355545044},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17637813091278076},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.12126955389976501}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7117018103599548},{"id":"https://openalex.org/C21200559","wikidata":"https://www.wikidata.org/wiki/Q7451068","display_name":"Sensitivity (control systems)","level":2,"score":0.6321938633918762},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.5277329683303833},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4650629162788391},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4539225101470947},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.43053171038627625},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4105827212333679},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4067310392856598},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.30080634355545044},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17637813091278076},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.12126955389976501},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/ddecs50862.2020.9095658","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs50862.2020.9095658","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:lirmm-03054134v1","is_oa":true,"landing_page_url":"https://hal-lirmm.ccsd.cnrs.fr/lirmm-03054134","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"DDECS 2020 - 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Apr 2020, Novi Sad, Serbia. pp.1-6, ⟨10.1109/DDECS50862.2020.9095658⟩","raw_type":"Conference papers"}],"best_oa_location":{"id":"pmh:oai:HAL:lirmm-03054134v1","is_oa":true,"landing_page_url":"https://hal-lirmm.ccsd.cnrs.fr/lirmm-03054134","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"DDECS 2020 - 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Apr 2020, Novi Sad, Serbia. pp.1-6, ⟨10.1109/DDECS50862.2020.9095658⟩","raw_type":"Conference papers"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":37,"referenced_works":["https://openalex.org/W1724438581","https://openalex.org/W1821462560","https://openalex.org/W1977556410","https://openalex.org/W2108598243","https://openalex.org/W2119144962","https://openalex.org/W2172166488","https://openalex.org/W2186615578","https://openalex.org/W2194775991","https://openalex.org/W2233116163","https://openalex.org/W2279098554","https://openalex.org/W2442974303","https://openalex.org/W2604319603","https://openalex.org/W2611289746","https://openalex.org/W2803549871","https://openalex.org/W2804193803","https://openalex.org/W2898992238","https://openalex.org/W2906043559","https://openalex.org/W2919358988","https://openalex.org/W2952432176","https://openalex.org/W2952746978","https://openalex.org/W2964258799","https://openalex.org/W2964299589","https://openalex.org/W3036882359","https://openalex.org/W3146781226","https://openalex.org/W4297813615","https://openalex.org/W4300081896","https://openalex.org/W6637709462","https://openalex.org/W6638523607","https://openalex.org/W6685405536","https://openalex.org/W6686509673","https://openalex.org/W6687483927","https://openalex.org/W6695314431","https://openalex.org/W6733877748","https://openalex.org/W6751769266","https://openalex.org/W6755261065","https://openalex.org/W6779896447","https://openalex.org/W6929263688"],"related_works":["https://openalex.org/W3014521742","https://openalex.org/W2617868873","https://openalex.org/W3204141294","https://openalex.org/W4306968100","https://openalex.org/W2171986175","https://openalex.org/W2170979950","https://openalex.org/W2501578203","https://openalex.org/W2113108952","https://openalex.org/W2040773997","https://openalex.org/W4389045579"],"abstract_inverted_index":{"The":[0],"following":[1],"topics":[2],"are":[3],"dealt":[4],"with:":[5],"embedded":[6],"systems;":[7,27],"logic":[8],"design;":[9,17],"CMOS":[10],"integrated":[11,15],"circuits;":[12],"neural":[13],"nets;":[14],"circuit":[16],"field":[18],"programmable":[19],"gate":[20],"arrays;":[21],"low-power":[22],"electronics;":[23],"formal":[24],"verification;":[25],"multiprocessing":[26],"Internet":[28],"of":[29],"Things.":[30]},"counts_by_year":[{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":6},{"year":2020,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}