{"id":"https://openalex.org/W2617185248","doi":"https://doi.org/10.1109/ddecs.2017.7934583","title":"Are XORs in logic synthesis really necessary?","display_name":"Are XORs in logic synthesis really necessary?","publication_year":2017,"publication_date":"2017-04-01","ids":{"openalex":"https://openalex.org/W2617185248","doi":"https://doi.org/10.1109/ddecs.2017.7934583","mag":"2617185248"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2017.7934583","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2017.7934583","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems (DDECS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049812666","display_name":"Ivo H\u00e1le\u010dek","orcid":"https://orcid.org/0000-0003-4544-4089"},"institutions":[{"id":"https://openalex.org/I44504214","display_name":"Czech Technical University in Prague","ror":"https://ror.org/03kqpb082","country_code":"CZ","type":"education","lineage":["https://openalex.org/I44504214"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"Ivo Halecek","raw_affiliation_strings":["Faculty of Information Technology, Czech Technical University in Prague, Prague, Czech Republic"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Information Technology, Czech Technical University in Prague, Prague, Czech Republic","institution_ids":["https://openalex.org/I44504214"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023119816","display_name":"Petr Fi\u0161er","orcid":"https://orcid.org/0000-0001-5306-6343"},"institutions":[{"id":"https://openalex.org/I44504214","display_name":"Czech Technical University in Prague","ror":"https://ror.org/03kqpb082","country_code":"CZ","type":"education","lineage":["https://openalex.org/I44504214"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"Petr Fiser","raw_affiliation_strings":["Faculty of Information Technology, Czech Technical University in Prague, Prague, Czech Republic"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Information Technology, Czech Technical University in Prague, Prague, Czech Republic","institution_ids":["https://openalex.org/I44504214"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101688195","display_name":"J. Schmidt","orcid":"https://orcid.org/0000-0001-7962-1712"},"institutions":[{"id":"https://openalex.org/I44504214","display_name":"Czech Technical University in Prague","ror":"https://ror.org/03kqpb082","country_code":"CZ","type":"education","lineage":["https://openalex.org/I44504214"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"Jan Schmidt","raw_affiliation_strings":["Faculty of Information Technology, Czech Technical University in Prague, Prague, Czech Republic"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Information Technology, Czech Technical University in Prague, Prague, Czech Republic","institution_ids":["https://openalex.org/I44504214"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I44504214"],"apc_list":null,"apc_paid":null,"fwci":1.9019,"has_fulltext":false,"cited_by_count":30,"citation_normalized_percentile":{"value":0.8772008,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"134","last_page":"139"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/rewriting","display_name":"Rewriting","score":0.8478364944458008},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7346842288970947},{"id":"https://openalex.org/keywords/xor-gate","display_name":"XOR gate","score":0.6908507943153381},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5552042126655579},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.5492616891860962},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5285462737083435},{"id":"https://openalex.org/keywords/representation","display_name":"Representation (politics)","score":0.5160260200500488},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.4390604496002197},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4292915165424347},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.32943195104599},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.32373493909835815}],"concepts":[{"id":"https://openalex.org/C154690210","wikidata":"https://www.wikidata.org/wiki/Q1668499","display_name":"Rewriting","level":2,"score":0.8478364944458008},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7346842288970947},{"id":"https://openalex.org/C28495749","wikidata":"https://www.wikidata.org/wiki/Q155516","display_name":"XOR gate","level":3,"score":0.6908507943153381},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5552042126655579},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.5492616891860962},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5285462737083435},{"id":"https://openalex.org/C2776359362","wikidata":"https://www.wikidata.org/wiki/Q2145286","display_name":"Representation (politics)","level":3,"score":0.5160260200500488},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.4390604496002197},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4292915165424347},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.32943195104599},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.32373493909835815},{"id":"https://openalex.org/C94625758","wikidata":"https://www.wikidata.org/wiki/Q7163","display_name":"Politics","level":2,"score":0.0},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.0},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ddecs.2017.7934583","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2017.7934583","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems (DDECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":35,"referenced_works":["https://openalex.org/W35668030","https://openalex.org/W1511688816","https://openalex.org/W1528837436","https://openalex.org/W1578592046","https://openalex.org/W1607177236","https://openalex.org/W1612810659","https://openalex.org/W1795892855","https://openalex.org/W1918485682","https://openalex.org/W1993937043","https://openalex.org/W1994143452","https://openalex.org/W1995135231","https://openalex.org/W2018094844","https://openalex.org/W2037931040","https://openalex.org/W2050779425","https://openalex.org/W2056040613","https://openalex.org/W2056693747","https://openalex.org/W2080267935","https://openalex.org/W2100465945","https://openalex.org/W2100921984","https://openalex.org/W2105761964","https://openalex.org/W2105972436","https://openalex.org/W2107762800","https://openalex.org/W2118615994","https://openalex.org/W2123710050","https://openalex.org/W2125188920","https://openalex.org/W2126693329","https://openalex.org/W2140132043","https://openalex.org/W2152406824","https://openalex.org/W2166755998","https://openalex.org/W2520093650","https://openalex.org/W6636505876","https://openalex.org/W6638277731","https://openalex.org/W6664435703","https://openalex.org/W6676077486","https://openalex.org/W6678797189"],"related_works":["https://openalex.org/W3208050235","https://openalex.org/W1999884834","https://openalex.org/W2008284187","https://openalex.org/W3140306724","https://openalex.org/W2170809665","https://openalex.org/W2163861263","https://openalex.org/W1991021576","https://openalex.org/W2134787045","https://openalex.org/W1979361505","https://openalex.org/W2098271200"],"abstract_inverted_index":{"This":[0],"paper":[1],"follows":[2],"recent":[3],"research":[4],"on":[5],"insufficient":[6],"synthesis":[7,40,52],"performance":[8],"for":[9],"XOR-intensive":[10],"circuits,":[11],"and":[12,41,66],"introduces":[13],"a":[14,19,50,71],"novel":[15],"logic":[16,39],"representation":[17],"with":[18],"native":[20],"support":[21],"of":[22,70],"XOR":[23],"gates,":[24],"the":[25,38,46,68],"XOR-AND-Inverter":[26],"Graphs":[27],"(XAIGs).":[28],"A":[29],"rewriting":[30,60],"algorithm":[31],"over":[32],"XAIG":[33,58],"has":[34],"been":[35],"implemented":[36],"in":[37,74],"optimization":[42],"package":[43],"ABC,":[44],"as":[45],"first":[47],"step":[48],"towards":[49],"complete":[51],"process.":[53],"The":[54],"results":[55],"show":[56],"that":[57],"based":[59],"can":[61],"help":[62],"to":[63],"discover":[64],"XORs":[65],"improves":[67],"area":[69],"mapped":[72],"network":[73],"some":[75],"cases.":[76]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":5},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
