{"id":"https://openalex.org/W2414307850","doi":"https://doi.org/10.1109/ddecs.2016.7482454","title":"Sequential test decompressors with fast variable wide spreading","display_name":"Sequential test decompressors with fast variable wide spreading","publication_year":2016,"publication_date":"2016-04-01","ids":{"openalex":"https://openalex.org/W2414307850","doi":"https://doi.org/10.1109/ddecs.2016.7482454","mag":"2414307850"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2016.7482454","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2016.7482454","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems (DDECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101706960","display_name":"Ond\u0159ej Nov\u00e1k","orcid":"https://orcid.org/0000-0002-3030-0616"},"institutions":[{"id":"https://openalex.org/I147009085","display_name":"Technical University of Liberec","ror":"https://ror.org/02jtk7k02","country_code":"CZ","type":"education","lineage":["https://openalex.org/I147009085"]}],"countries":["CZ"],"is_corresponding":true,"raw_author_name":"O. Novak","raw_affiliation_strings":["FMMIS, Technical University in Liberec, Liberec, Czech Republic"],"affiliations":[{"raw_affiliation_string":"FMMIS, Technical University in Liberec, Liberec, Czech Republic","institution_ids":["https://openalex.org/I147009085"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047871386","display_name":"Ji\u0159\u00ed Jen\u00ed\u010dek","orcid":"https://orcid.org/0000-0001-6556-8180"},"institutions":[{"id":"https://openalex.org/I147009085","display_name":"Technical University of Liberec","ror":"https://ror.org/02jtk7k02","country_code":"CZ","type":"education","lineage":["https://openalex.org/I147009085"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"J. Jenicek","raw_affiliation_strings":["FMMIS, Technical University in Liberec, Liberec, Czech Republic"],"affiliations":[{"raw_affiliation_string":"FMMIS, Technical University in Liberec, Liberec, Czech Republic","institution_ids":["https://openalex.org/I147009085"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5066149539","display_name":"Martin Rozkovec","orcid":"https://orcid.org/0000-0001-5221-616X"},"institutions":[{"id":"https://openalex.org/I147009085","display_name":"Technical University of Liberec","ror":"https://ror.org/02jtk7k02","country_code":"CZ","type":"education","lineage":["https://openalex.org/I147009085"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"M. Rozkovec","raw_affiliation_strings":["FMMIS, Technical University in Liberec, Liberec, Czech Republic"],"affiliations":[{"raw_affiliation_string":"FMMIS, Technical University in Liberec, Liberec, Czech Republic","institution_ids":["https://openalex.org/I147009085"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5101706960"],"corresponding_institution_ids":["https://openalex.org/I147009085"],"apc_list":null,"apc_paid":null,"fwci":0.3153,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.55360166,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9860000014305115,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scan-chain","display_name":"Scan chain","score":0.7868167757987976},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7191594839096069},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.6176669001579285},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5977807641029358},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5464011430740356},{"id":"https://openalex.org/keywords/encoding","display_name":"Encoding (memory)","score":0.5338730812072754},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.5124655365943909},{"id":"https://openalex.org/keywords/reset","display_name":"Reset (finance)","score":0.44400227069854736},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3999807834625244},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.38197168707847595},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3607648015022278},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1809464991092682},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.14410096406936646},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.1318511664867401},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.11625650525093079},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10079565644264221}],"concepts":[{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.7868167757987976},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7191594839096069},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.6176669001579285},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5977807641029358},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5464011430740356},{"id":"https://openalex.org/C125411270","wikidata":"https://www.wikidata.org/wiki/Q18653","display_name":"Encoding (memory)","level":2,"score":0.5338730812072754},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.5124655365943909},{"id":"https://openalex.org/C2779795794","wikidata":"https://www.wikidata.org/wiki/Q7315343","display_name":"Reset (finance)","level":2,"score":0.44400227069854736},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3999807834625244},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.38197168707847595},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3607648015022278},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1809464991092682},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.14410096406936646},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.1318511664867401},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.11625650525093079},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10079565644264221},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C106159729","wikidata":"https://www.wikidata.org/wiki/Q2294553","display_name":"Financial economics","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ddecs.2016.7482454","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2016.7482454","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems (DDECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1571166580","https://openalex.org/W1991645253","https://openalex.org/W2003936936","https://openalex.org/W2006119235","https://openalex.org/W2013301215","https://openalex.org/W2023158154","https://openalex.org/W2045356889","https://openalex.org/W2101900253","https://openalex.org/W2102404182","https://openalex.org/W2105282021","https://openalex.org/W2130722990","https://openalex.org/W2135627440","https://openalex.org/W2146667976","https://openalex.org/W2149093111","https://openalex.org/W2153126169","https://openalex.org/W2153702200","https://openalex.org/W2159871346","https://openalex.org/W4234998257"],"related_works":["https://openalex.org/W1974621628","https://openalex.org/W2118952760","https://openalex.org/W2075356617","https://openalex.org/W2274367941","https://openalex.org/W2390529848","https://openalex.org/W2763030692","https://openalex.org/W2073042086","https://openalex.org/W2143881398","https://openalex.org/W2092894550","https://openalex.org/W2789883751"],"abstract_inverted_index":{"Usually,":[0],"test":[1,13,26,42,115,119,136],"pattern":[2,14,120],"decompressors":[3,127],"with":[4,25,128],"dynamic":[5],"reseeding":[6],"are":[7,22],"reset":[8],"before":[9],"starting":[10],"a":[11,95,98,140],"new":[12],"decoding.":[15],"The":[16,117],"first":[17],"few":[18],"scan":[19,90],"chain":[20,91],"slices":[21],"then":[23],"filled":[24],"vectors":[27],"that":[28,49,107],"have":[29,47],"lower":[30],"decodability":[31],"as":[32,74,76],"the":[33,41,55,61,64,82,89,110,114,123,135,144],"number":[34,56],"of":[35,57,81,125,143],"free":[36,58,111],"variables":[37,59,112],"is":[38,51],"limited":[39],"by":[40,68],"access":[43],"mechanism":[44],"bandwidth.":[45],"We":[46,93],"found":[48],"it":[50,133],"possible":[52,77,141],"to":[53,139],"increase":[54],"in":[60],"equations":[62],"describing":[63],"care":[65],"bits":[66,84],"encoding":[67],"fast":[69],"creating":[70],"and":[71,85,102,132],"wide":[72],"spreading":[73],"many":[75],"independent":[78],"linear":[79,100],"combinations":[80],"tester":[83],"using":[86],"them":[87],"for":[88],"loading.":[92],"propose":[94],"decompressor":[96,101,121,145],"combining":[97],"combinational":[99],"an":[103],"LFSR":[104],"like":[105],"automaton":[106],"effectively":[108],"distributes":[109],"within":[113],"pattern.":[116],"proposed":[118],"outperforms":[122],"de-codability":[124],"other":[126],"similar":[129],"hardware":[130],"overhead":[131],"reduces":[134],"time":[137],"due":[138],"reduction":[142],"preloading.":[146]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
