{"id":"https://openalex.org/W1550280164","doi":"https://doi.org/10.1109/ddecs.2015.33","title":"FPGA Prototyping and Accelerated Verification of ASIPs","display_name":"FPGA Prototyping and Accelerated Verification of ASIPs","publication_year":2015,"publication_date":"2015-04-01","ids":{"openalex":"https://openalex.org/W1550280164","doi":"https://doi.org/10.1109/ddecs.2015.33","mag":"1550280164"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2015.33","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2015.33","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5091193155","display_name":"Jakub Podiv\u00ednsk\u00fd","orcid":null},"institutions":[{"id":"https://openalex.org/I60587646","display_name":"Brno University of Technology","ror":"https://ror.org/03613d656","country_code":"CZ","type":"education","lineage":["https://openalex.org/I60587646"]}],"countries":["CZ"],"is_corresponding":true,"raw_author_name":"Jakub Podivinsky","raw_affiliation_strings":["Faculty of Information Technology, Brno University of Technology, Brno, Czech Republic","Fac. of Inf. Technol., Brno Univ. of Technol., Brno, Czech Republic"],"affiliations":[{"raw_affiliation_string":"Faculty of Information Technology, Brno University of Technology, Brno, Czech Republic","institution_ids":["https://openalex.org/I60587646"]},{"raw_affiliation_string":"Fac. of Inf. Technol., Brno Univ. of Technol., Brno, Czech Republic","institution_ids":["https://openalex.org/I60587646"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070576985","display_name":"Marcela imkova","orcid":null},"institutions":[{"id":"https://openalex.org/I60587646","display_name":"Brno University of Technology","ror":"https://ror.org/03613d656","country_code":"CZ","type":"education","lineage":["https://openalex.org/I60587646"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"Marcela imkova","raw_affiliation_strings":["Vysoke uceni technicke v Brne, Brno, Moravskoslezsk\u00c3\u00bd, CZ","Fac. of Inf. Technol., Brno Univ. of Technol., Brno, Czech Republic"],"affiliations":[{"raw_affiliation_string":"Vysoke uceni technicke v Brne, Brno, Moravskoslezsk\u00c3\u00bd, CZ","institution_ids":["https://openalex.org/I60587646"]},{"raw_affiliation_string":"Fac. of Inf. Technol., Brno Univ. of Technol., Brno, Czech Republic","institution_ids":["https://openalex.org/I60587646"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055608790","display_name":"Ondrej Cekan","orcid":null},"institutions":[{"id":"https://openalex.org/I60587646","display_name":"Brno University of Technology","ror":"https://ror.org/03613d656","country_code":"CZ","type":"education","lineage":["https://openalex.org/I60587646"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"Ondrej Cekan","raw_affiliation_strings":["Faculty of Information Technology, Brno University of Technology, Brno, Czech Republic","Fac. of Inf. Technol., Brno Univ. of Technol., Brno, Czech Republic"],"affiliations":[{"raw_affiliation_string":"Faculty of Information Technology, Brno University of Technology, Brno, Czech Republic","institution_ids":["https://openalex.org/I60587646"]},{"raw_affiliation_string":"Fac. of Inf. Technol., Brno Univ. of Technol., Brno, Czech Republic","institution_ids":["https://openalex.org/I60587646"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040514508","display_name":"Zden\u011bk Kot\u00e1sek","orcid":null},"institutions":[{"id":"https://openalex.org/I60587646","display_name":"Brno University of Technology","ror":"https://ror.org/03613d656","country_code":"CZ","type":"education","lineage":["https://openalex.org/I60587646"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"Zdenek Kotasek","raw_affiliation_strings":["Faculty of Information Technology, Brno University of Technology, Brno, Czech Republic","Fac. of Inf. Technol., Brno Univ. of Technol., Brno, Czech Republic"],"affiliations":[{"raw_affiliation_string":"Faculty of Information Technology, Brno University of Technology, Brno, Czech Republic","institution_ids":["https://openalex.org/I60587646"]},{"raw_affiliation_string":"Fac. of Inf. Technol., Brno Univ. of Technol., Brno, Czech Republic","institution_ids":["https://openalex.org/I60587646"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5091193155"],"corresponding_institution_ids":["https://openalex.org/I60587646"],"apc_list":null,"apc_paid":null,"fwci":1.0516,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.77464742,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"abs 1002 134","issue":null,"first_page":"145","last_page":"148"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/intelligent-verification","display_name":"Intelligent verification","score":0.8364943265914917},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8080626130104065},{"id":"https://openalex.org/keywords/high-level-verification","display_name":"High-level verification","score":0.7942646741867065},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.7797759771347046},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.742048978805542},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7276750802993774},{"id":"https://openalex.org/keywords/verification","display_name":"Verification","score":0.6821466684341431},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6411840915679932},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.6156392693519592},{"id":"https://openalex.org/keywords/software-verification","display_name":"Software verification","score":0.574489414691925},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.5695421695709229},{"id":"https://openalex.org/keywords/runtime-verification","display_name":"Runtime verification","score":0.563016414642334},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4771425426006317},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.43982771039009094},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.30745530128479004},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.21557369828224182},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.14741787314414978},{"id":"https://openalex.org/keywords/software-construction","display_name":"Software construction","score":0.0841594934463501},{"id":"https://openalex.org/keywords/software-development","display_name":"Software development","score":0.08102878928184509}],"concepts":[{"id":"https://openalex.org/C3406870","wikidata":"https://www.wikidata.org/wiki/Q6044160","display_name":"Intelligent verification","level":5,"score":0.8364943265914917},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8080626130104065},{"id":"https://openalex.org/C187250869","wikidata":"https://www.wikidata.org/wiki/Q5754573","display_name":"High-level verification","level":5,"score":0.7942646741867065},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.7797759771347046},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.742048978805542},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7276750802993774},{"id":"https://openalex.org/C142284323","wikidata":"https://www.wikidata.org/wiki/Q7921323","display_name":"Verification","level":5,"score":0.6821466684341431},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6411840915679932},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.6156392693519592},{"id":"https://openalex.org/C33054407","wikidata":"https://www.wikidata.org/wiki/Q6504747","display_name":"Software verification","level":5,"score":0.574489414691925},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.5695421695709229},{"id":"https://openalex.org/C202973057","wikidata":"https://www.wikidata.org/wiki/Q7380130","display_name":"Runtime verification","level":3,"score":0.563016414642334},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4771425426006317},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.43982771039009094},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.30745530128479004},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.21557369828224182},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.14741787314414978},{"id":"https://openalex.org/C186846655","wikidata":"https://www.wikidata.org/wiki/Q3398377","display_name":"Software construction","level":4,"score":0.0841594934463501},{"id":"https://openalex.org/C529173508","wikidata":"https://www.wikidata.org/wiki/Q638608","display_name":"Software development","level":3,"score":0.08102878928184509}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ddecs.2015.33","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2015.33","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W25906867","https://openalex.org/W1463133470","https://openalex.org/W2094342270","https://openalex.org/W2095129947","https://openalex.org/W2161028355","https://openalex.org/W2166915430","https://openalex.org/W2301822014","https://openalex.org/W6683924383","https://openalex.org/W6697800800"],"related_works":["https://openalex.org/W2361881307","https://openalex.org/W2392047570","https://openalex.org/W2035244079","https://openalex.org/W4205300843","https://openalex.org/W3036403349","https://openalex.org/W3120172095","https://openalex.org/W4301348901","https://openalex.org/W2350806125","https://openalex.org/W2535719568","https://openalex.org/W1550280164"],"abstract_inverted_index":{"In":[0],"current":[1],"SoC":[2,18],"verification,":[3],"the":[4,27,81,87],"trend":[5],"is":[6,25,52],"to":[7,14,20,35,54,86],"create":[8],"verification":[9,38,76,83,102,107],"solutions":[10],"that":[11,26,51],"are":[12],"tailored":[13],"specific":[15,21,129],"issues":[16],"in":[17,123,127],"or":[19,43],"architectures.":[22],"The":[23],"reason":[24],"complexity":[28],"of":[29,77,89,101,106],"these":[30,78],"systems":[31,65,79],"makes":[32,114],"it":[33],"difficult":[34],"use":[36],"general":[37],"approaches":[39],"such":[40],"as":[41],"formal":[42],"simulation-based":[44],"verification.":[45],"This":[46],"paper":[47],"presents":[48],"a":[49,110],"solution":[50,116],"targeted":[53],"one":[55],"particular":[56],"area":[57],"-":[58],"Application-Specific":[59],"Instruction-Set":[60],"Processors":[61],"(ASIP)":[62],"and":[63,74,104,119],"multi-processor":[64],"containing":[66],"several":[67],"ASIPs.":[68],"We":[69],"propose":[70],"automated":[71],"FPGA":[72],"prototyping":[73],"accelerated":[75,82],"while":[80],"environment":[84],"corresponds":[85],"principles":[88],"UVM":[90],"(Universal":[91],"Verification":[92],"Methodology)":[93],"therefore":[94],"can":[95],"easily":[96],"be":[97],"integrated.":[98],"Automated":[99],"generation":[100],"environments":[103],"acceleration":[105],"runnning":[108],"on":[109],"real":[111],"hardware":[112,130],"platform":[113],"this":[115],"very":[117],"unique":[118],"beneficial,":[120],"not":[121],"only":[122],"speed,":[124],"but":[125],"also":[126],"debugging":[128],"issues.":[131]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
