{"id":"https://openalex.org/W2106992483","doi":"https://doi.org/10.1109/ddecs.2011.5783109","title":"Optimized embedded memory diagnosis","display_name":"Optimized embedded memory diagnosis","publication_year":2011,"publication_date":"2011-04-01","ids":{"openalex":"https://openalex.org/W2106992483","doi":"https://doi.org/10.1109/ddecs.2011.5783109","mag":"2106992483"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2011.5783109","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2011.5783109","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101437140","display_name":"Maur\u00edcio Carvalho","orcid":"https://orcid.org/0000-0002-4877-4609"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"M. de Carvalho","raw_affiliation_strings":["Politecnico di Torino, Dip. di Automatica e Informatica, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Torino, Dip. di Automatica e Informatica, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049430681","display_name":"Paolo Bernardi","orcid":"https://orcid.org/0000-0002-0985-9327"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"P. Bernardi","raw_affiliation_strings":["Dip. di Automatica e Informatica, Politecnico di Torino, Torino, Italy","Politecnico di Torino, Dip. di Automatica e Informatica, Italy"],"affiliations":[{"raw_affiliation_string":"Dip. di Automatica e Informatica, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Politecnico di Torino, Dip. di Automatica e Informatica, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058555274","display_name":"M. Sonza Reorda","orcid":"https://orcid.org/0000-0003-2899-7669"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Sonza Reorda","raw_affiliation_strings":["Dip. di Automatica e Informatica, Politecnico di Torino, Torino, Italy","Politecnico di Torino, Dip. di Automatica e Informatica, Italy"],"affiliations":[{"raw_affiliation_string":"Dip. di Automatica e Informatica, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Politecnico di Torino, Dip. di Automatica e Informatica, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032071290","display_name":"N. Campanelli","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"N. Campanelli","raw_affiliation_strings":["NplusT Semiconductor Application Center, Montecastrilli, TR, Italy","NplusT, Semiconductor Application Center, Montecastrilli (TR), Italy"],"affiliations":[{"raw_affiliation_string":"NplusT Semiconductor Application Center, Montecastrilli, TR, Italy","institution_ids":[]},{"raw_affiliation_string":"NplusT, Semiconductor Application Center, Montecastrilli (TR), Italy","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089972415","display_name":"T. Kerekes","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"T. Kerekes","raw_affiliation_strings":["NplusT Semiconductor Application Center, Montecastrilli, TR, Italy","NplusT, Semiconductor Application Center, Montecastrilli (TR), Italy"],"affiliations":[{"raw_affiliation_string":"NplusT Semiconductor Application Center, Montecastrilli, TR, Italy","institution_ids":[]},{"raw_affiliation_string":"NplusT, Semiconductor Application Center, Montecastrilli (TR), Italy","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024226992","display_name":"D. Appello","orcid":"https://orcid.org/0000-0001-8178-2785"},"institutions":[{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"D. Appello","raw_affiliation_strings":["STMicroelectronics, Agrate Brianza, MI, Italy","STMicroelectronics, Agrate Brianza (MI), Italy"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Agrate Brianza, MI, Italy","institution_ids":["https://openalex.org/I4210154781"]},{"raw_affiliation_string":"STMicroelectronics, Agrate Brianza (MI), Italy","institution_ids":["https://openalex.org/I4210154781"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109064750","display_name":"M. Barone","orcid":null},"institutions":[{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Barone","raw_affiliation_strings":["STMicroelectronics, Agrate Brianza, MI, Italy","STMicroelectronics, Agrate Brianza (MI), Italy"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Agrate Brianza, MI, Italy","institution_ids":["https://openalex.org/I4210154781"]},{"raw_affiliation_string":"STMicroelectronics, Agrate Brianza (MI), Italy","institution_ids":["https://openalex.org/I4210154781"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043908290","display_name":"Vincenzo Tancorre","orcid":"https://orcid.org/0000-0001-7959-0784"},"institutions":[{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"V. Tancorre","raw_affiliation_strings":["STMicroelectronics, Agrate Brianza, MI, Italy","STMicroelectronics, Agrate Brianza (MI), Italy"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Agrate Brianza, MI, Italy","institution_ids":["https://openalex.org/I4210154781"]},{"raw_affiliation_string":"STMicroelectronics, Agrate Brianza (MI), Italy","institution_ids":["https://openalex.org/I4210154781"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5019139311","display_name":"M. Terzi","orcid":null},"institutions":[{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Terzi","raw_affiliation_strings":["STMicroelectronics, Agrate Brianza, MI, Italy","STMicroelectronics, Agrate Brianza (MI), Italy"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Agrate Brianza, MI, Italy","institution_ids":["https://openalex.org/I4210154781"]},{"raw_affiliation_string":"STMicroelectronics, Agrate Brianza (MI), Italy","institution_ids":["https://openalex.org/I4210154781"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":9,"corresponding_author_ids":["https://openalex.org/A5101437140"],"corresponding_institution_ids":["https://openalex.org/I177477856"],"apc_list":null,"apc_paid":null,"fwci":0.7703,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.74102375,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"347","last_page":"352"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7017164826393127},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6840727925300598},{"id":"https://openalex.org/keywords/bitmap","display_name":"Bitmap","score":0.5910341739654541},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5821166634559631},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5202085375785828},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.47898173332214355},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.4273780584335327},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3866768479347229},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.1563790738582611}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7017164826393127},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6840727925300598},{"id":"https://openalex.org/C3115412","wikidata":"https://www.wikidata.org/wiki/Q1194708","display_name":"Bitmap","level":2,"score":0.5910341739654541},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5821166634559631},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5202085375785828},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.47898173332214355},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.4273780584335327},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3866768479347229},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.1563790738582611},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/ddecs.2011.5783109","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2011.5783109","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:porto.polito.it:2460411","is_oa":false,"landing_page_url":"http://porto.polito.it/2460411/","pdf_url":null,"source":{"id":"https://openalex.org/S4306402038","display_name":"PORTO Publications Open Repository TOrino (Politecnico di Torino)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I177477856","host_organization_name":"Politecnico di Torino","host_organization_lineage":["https://openalex.org/I177477856"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.5699999928474426}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W289624287","https://openalex.org/W2021130660","https://openalex.org/W2106935654","https://openalex.org/W2131192688","https://openalex.org/W2164333395","https://openalex.org/W2169517241","https://openalex.org/W6655584797"],"related_works":["https://openalex.org/W17155033","https://openalex.org/W2350456333","https://openalex.org/W2101993108","https://openalex.org/W2356608866","https://openalex.org/W2355840328","https://openalex.org/W1975966184","https://openalex.org/W3207760230","https://openalex.org/W1496222301","https://openalex.org/W2137246017","https://openalex.org/W2119025037"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"an":[3,66],"optimized":[4],"embedded":[5,79],"memory":[6,81],"diagnosis":[7],"flow":[8,24],"that":[9],"exploits":[10],"many":[11,28],"levels":[12],"of":[13,27,60],"knowledge":[14],"to":[15,43,49,95,104],"produce":[16],"accurate":[17],"failure":[18,31],"hypothesis.":[19],"The":[20,58],"proposed":[21],"post-processing":[22],"analysis":[23],"is":[25,63,102],"composed":[26],"steps":[29],"investigating":[30],"shapes":[32],"as":[33,35],"well":[34],"cell":[36],"fail":[37],"syndromes,":[38],"and":[39,110],"includes":[40,78],"advanced":[41],"techniques":[42],"tackle":[44],"incomplete":[45],"data":[46],"possibly":[47],"due":[48],"tester":[50],"noise":[51],"and/or":[52],"by":[53,75],"faults":[54],"showing":[55],"intermittent":[56],"effects.":[57],"effectiveness":[59],"the":[61,107],"technique":[62],"demonstrated":[64],"on":[65,106],"automotive-oriented":[67],"System-on-Chip":[68],"(SoC)":[69],"manufactured":[70],"in":[71],"a":[72,85,91],"90nm":[73],"technology":[74],"STMicroelectronics,":[76],"which":[77],"SRAM":[80],"cores":[82],"tested":[83],"using":[84],"programmable":[86],"BIST.":[87],"Scrambled":[88],"BITMAPS":[89],"gives":[90],"visual":[92],"feedback":[93],"leading":[94],"quick":[96],"physical":[97],"defect":[98],"identification.":[99],"Such":[100],"research":[101],"relevant":[103],"aid":[105],"manufacturing,":[108],"material":[109],"process":[111],"enhancements":[112],"raising":[113],"silicon":[114],"yield.":[115]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2012,"cited_by_count":3}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
