{"id":"https://openalex.org/W2122439617","doi":"https://doi.org/10.1109/ddecs.2010.5491792","title":"Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects","display_name":"Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects","publication_year":2010,"publication_date":"2010-04-01","ids":{"openalex":"https://openalex.org/W2122439617","doi":"https://doi.org/10.1109/ddecs.2010.5491792","mag":"2122439617"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2010.5491792","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2010.5491792","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007028121","display_name":"Tetsuya Iizuka","orcid":"https://orcid.org/0000-0002-1512-4714"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Tetsuya Iizuka","raw_affiliation_strings":["VLSI Design and Education Center (VDEC), University of Tokyo, Bunkyo, Tokyo, Japan","VLSI Design and Education Center (VDEC), University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan"],"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center (VDEC), University of Tokyo, Bunkyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"VLSI Design and Education Center (VDEC), University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071803491","display_name":"Toru Nakura","orcid":"https://orcid.org/0000-0001-5945-3918"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Toru Nakura","raw_affiliation_strings":["VLSI Design and Education Center (VDEC), University of Tokyo, Bunkyo, Tokyo, Japan","VLSI Design and Education Center (VDEC), University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan"],"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center (VDEC), University of Tokyo, Bunkyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"VLSI Design and Education Center (VDEC), University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028680447","display_name":"Kunihiro Asada","orcid":"https://orcid.org/0000-0002-1150-0241"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kunihiro Asada","raw_affiliation_strings":["Tokyo Daigaku, Bunkyo-ku, Tokyo, JP","VLSI Design and Education Center (VDEC), University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan"],"affiliations":[{"raw_affiliation_string":"Tokyo Daigaku, Bunkyo-ku, Tokyo, JP","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"VLSI Design and Education Center (VDEC), University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5007028121"],"corresponding_institution_ids":["https://openalex.org/I74801974"],"apc_list":null,"apc_paid":null,"fwci":2.5978,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.90361472,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"167","last_page":"172"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.9461992383003235},{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.9354825019836426},{"id":"https://openalex.org/keywords/ring-oscillator","display_name":"Ring oscillator","score":0.9134243130683899},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5859646797180176},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4895671308040619},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4799816310405731},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4752597510814667},{"id":"https://openalex.org/keywords/pulse","display_name":"Pulse (music)","score":0.4482623338699341},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.43873071670532227},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.4339383840560913},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4177425503730774},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.35669106245040894},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.25980105996131897},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.2540145814418793},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2503974437713623},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1645798683166504}],"concepts":[{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.9461992383003235},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.9354825019836426},{"id":"https://openalex.org/C104111718","wikidata":"https://www.wikidata.org/wiki/Q2153973","display_name":"Ring oscillator","level":3,"score":0.9134243130683899},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5859646797180176},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4895671308040619},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4799816310405731},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4752597510814667},{"id":"https://openalex.org/C2780167933","wikidata":"https://www.wikidata.org/wiki/Q1550652","display_name":"Pulse (music)","level":3,"score":0.4482623338699341},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.43873071670532227},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.4339383840560913},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4177425503730774},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.35669106245040894},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.25980105996131897},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.2540145814418793},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2503974437713623},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1645798683166504},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ddecs.2010.5491792","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2010.5491792","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.44999998807907104}],"awards":[],"funders":[{"id":"https://openalex.org/F4320322832","display_name":"University of Tokyo","ror":"https://ror.org/057zh3y96"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1986751201","https://openalex.org/W2031068066","https://openalex.org/W2042809000","https://openalex.org/W2066698193","https://openalex.org/W2104010258","https://openalex.org/W2115150721","https://openalex.org/W2130719086","https://openalex.org/W2134869654","https://openalex.org/W2151218494","https://openalex.org/W2154221003","https://openalex.org/W2159971659","https://openalex.org/W6646955768","https://openalex.org/W6666855326"],"related_works":["https://openalex.org/W4386261925","https://openalex.org/W2048420745","https://openalex.org/W2082944690","https://openalex.org/W2263373136","https://openalex.org/W1914349328","https://openalex.org/W2160067645","https://openalex.org/W2745127909","https://openalex.org/W2537099411","https://openalex.org/W3104408177","https://openalex.org/W2947980285"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3,69],"propose":[4],"an":[5],"all-digital":[6],"process":[7,27,99,119],"variability":[8,28,120],"and":[9,44,74,78,85,137],"aging":[10,129],"monitor":[11],"which":[12,38,64],"utilizes":[13],"a":[14,19,31,35,45,60],"simple":[15,61],"buffer":[16,42],"ring":[17,43,62],"with":[18,59],"pulse":[20,37,51],"counter.":[21],"The":[22,89,108],"proposed":[23,55,105,109],"circuit":[24,56,94],"monitors":[25,65,80],"the":[26,41,50,54,72,81,93,101,104,117,125],"according":[29],"to":[30],"count":[32],"number":[33],"of":[34,83,92,103,128],"single":[36],"propagates":[39],"on":[40,96],"fixed":[46],"logic":[47],"level":[48],"after":[49],"vanishes.":[52],"Using":[53],"in":[57],"combination":[58],"oscillator":[63],"its":[66],"oscillation":[67],"period,":[68],"can":[70,79],"calculate":[71],"rise":[73],"fall":[75],"delay":[76],"values":[77],"variabilities":[82],"PMOS":[84],"NMOS":[86],"devices":[87],"independently.":[88],"experimental":[90],"results":[91],"simulation":[95],"65nm":[97],"CMOS":[98],"indicate":[100],"feasibility":[102],"monitoring":[106,110,121,127],"circuit.":[107],"technique":[111],"is":[112],"suitable":[113],"not":[114],"only":[115],"for":[116,124],"on-chip":[118],"but":[122],"also":[123],"infield":[126],"effects":[130],"such":[131],"as":[132],"negative":[133],"bias":[134],"instability":[135],"(NBTI)":[136],"channel":[138],"hot":[139],"carrier":[140],"(CHC).":[141]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}