{"id":"https://openalex.org/W2018607512","doi":"https://doi.org/10.1109/ddecs.2010.5491756","title":"Synthesis of asynchronous monitors for critical electronic systems","display_name":"Synthesis of asynchronous monitors for critical electronic systems","publication_year":2010,"publication_date":"2010-04-01","ids":{"openalex":"https://openalex.org/W2018607512","doi":"https://doi.org/10.1109/ddecs.2010.5491756","mag":"2018607512"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2010.5491756","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2010.5491756","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007418105","display_name":"Alexandre Porcher","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I899635006","display_name":"Universit\u00e9 Grenoble Alpes","ror":"https://ror.org/02rx3b187","country_code":"FR","type":"education","lineage":["https://openalex.org/I899635006"]},{"id":"https://openalex.org/I177483745","display_name":"Universit\u00e9 Joseph Fourier","ror":"https://ror.org/02aj0kh94","country_code":"FR","type":"education","lineage":["https://openalex.org/I177483745"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Alexandre Porcher","raw_affiliation_strings":["TIMA Laboratory, INPG/UJF/CNRS, Grenoble, France","TIMA Laboratory, INPG/UJF/CNRS, 46 Avenue F. Viallet, 38031 Grenoble Cedex, France"],"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, INPG/UJF/CNRS, Grenoble, France","institution_ids":["https://openalex.org/I4210087012","https://openalex.org/I177483745","https://openalex.org/I899635006","https://openalex.org/I1294671590"]},{"raw_affiliation_string":"TIMA Laboratory, INPG/UJF/CNRS, 46 Avenue F. Viallet, 38031 Grenoble Cedex, France","institution_ids":["https://openalex.org/I177483745","https://openalex.org/I1294671590"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067330751","display_name":"Katell Morin-Allory","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I177483745","display_name":"Universit\u00e9 Joseph Fourier","ror":"https://ror.org/02aj0kh94","country_code":"FR","type":"education","lineage":["https://openalex.org/I177483745"]},{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I899635006","display_name":"Universit\u00e9 Grenoble Alpes","ror":"https://ror.org/02rx3b187","country_code":"FR","type":"education","lineage":["https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Katell Morin-Allory","raw_affiliation_strings":["TIMA Laboratory, INPG/UJF/CNRS, Grenoble, France","TIMA Laboratory, INPG/UJF/CNRS, 46 Avenue F. Viallet, 38031 Grenoble Cedex, France"],"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, INPG/UJF/CNRS, Grenoble, France","institution_ids":["https://openalex.org/I4210087012","https://openalex.org/I177483745","https://openalex.org/I899635006","https://openalex.org/I1294671590"]},{"raw_affiliation_string":"TIMA Laboratory, INPG/UJF/CNRS, 46 Avenue F. Viallet, 38031 Grenoble Cedex, France","institution_ids":["https://openalex.org/I177483745","https://openalex.org/I1294671590"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038428972","display_name":"Laurent Fesquet","orcid":"https://orcid.org/0000-0002-6045-8510"},"institutions":[{"id":"https://openalex.org/I899635006","display_name":"Universit\u00e9 Grenoble Alpes","ror":"https://ror.org/02rx3b187","country_code":"FR","type":"education","lineage":["https://openalex.org/I899635006"]},{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I177483745","display_name":"Universit\u00e9 Joseph Fourier","ror":"https://ror.org/02aj0kh94","country_code":"FR","type":"education","lineage":["https://openalex.org/I177483745"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Laurent Fesquet","raw_affiliation_strings":["TIMA Laboratory, INPG/UJF/CNRS, Grenoble, France","TIMA Laboratory, INPG/UJF/CNRS, 46 Avenue F. Viallet, 38031 Grenoble Cedex, France"],"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, INPG/UJF/CNRS, Grenoble, France","institution_ids":["https://openalex.org/I4210087012","https://openalex.org/I177483745","https://openalex.org/I899635006","https://openalex.org/I1294671590"]},{"raw_affiliation_string":"TIMA Laboratory, INPG/UJF/CNRS, 46 Avenue F. Viallet, 38031 Grenoble Cedex, France","institution_ids":["https://openalex.org/I177483745","https://openalex.org/I1294671590"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5007418105"],"corresponding_institution_ids":["https://openalex.org/I1294671590","https://openalex.org/I177483745","https://openalex.org/I4210087012","https://openalex.org/I899635006"],"apc_list":null,"apc_paid":null,"fwci":0.512,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.66303326,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"1855","issue":null,"first_page":"329","last_page":"334"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.9000884890556335},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7481707334518433},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6425755023956299},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4852428436279297},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4591251611709595},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.40210822224617004},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.179475337266922},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1553838551044464},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15359008312225342}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.9000884890556335},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7481707334518433},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6425755023956299},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4852428436279297},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4591251611709595},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.40210822224617004},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.179475337266922},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1553838551044464},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15359008312225342}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/ddecs.2010.5491756","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2010.5491756","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-00517676v1","is_oa":false,"landing_page_url":"https://hal.science/hal-00517676","pdf_url":null,"source":{"id":"https://openalex.org/S4406922461","display_name":"SPIRE - Sciences Po Institutional REpository","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'10), Apr 2010, Vienna, Austria. pp.329 - 334, ⟨10.1109/DDECS.2010.5491756⟩","raw_type":"Conference papers"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W105423953","https://openalex.org/W1514480347","https://openalex.org/W1545186619","https://openalex.org/W1597832877","https://openalex.org/W1984272421","https://openalex.org/W1996109622","https://openalex.org/W2071589114","https://openalex.org/W2103931510","https://openalex.org/W2115965729","https://openalex.org/W2121316343","https://openalex.org/W2123613958","https://openalex.org/W2123732432","https://openalex.org/W2150872535","https://openalex.org/W2161501894","https://openalex.org/W2168938812","https://openalex.org/W2487142227","https://openalex.org/W2504260463","https://openalex.org/W4213400502","https://openalex.org/W4285719527","https://openalex.org/W6646492351"],"related_works":["https://openalex.org/W2116677773","https://openalex.org/W2155261584","https://openalex.org/W2111241003","https://openalex.org/W2584231425","https://openalex.org/W2150611273","https://openalex.org/W4207086172","https://openalex.org/W2096844293","https://openalex.org/W2363944576","https://openalex.org/W2351041855","https://openalex.org/W2570254841"],"abstract_inverted_index":{"Monitors":[0],"are":[1,36],"small":[2],"IPs":[3],"that":[4,11],"check":[5],"critical":[6],"systems,":[7],"such":[8],"as":[9],"radio-altimeters":[10],"on-line":[12],"control":[13],"the":[14,40],"landing":[15],"phase":[16],"in":[17,46,61],"modern":[18],"planes.":[19],"It":[20],"is":[21],"essential":[22],"to":[23,39],"get":[24],"correct":[25],"information":[26],"and":[27,55,74,86,92],"avoid":[28],"erroneous":[29],"messages":[30],"from":[31,76],"these":[32],"monitors.":[33],"Asynchronous":[34],"monitors":[35,70,82],"very":[37],"robust":[38],"environment":[41],"variations;":[42],"they":[43],"remain":[44],"functional":[45],"a":[47,62,89,93],"wide":[48],"range":[49],"of":[50],"power":[51],"supplies":[52],"or":[53],"temperatures,":[54],"can":[56,71],"reliably":[57],"monitor":[58],"synchronous":[59],"circuits":[60],"harsh":[63],"environment.":[64],"This":[65],"paper":[66],"discusses":[67],"how":[68],"asynchronous":[69],"be":[72],"modeled":[73],"generated":[75],"Property":[77],"Specification":[78],"Language":[79],"(PSL).":[80],"These":[81],"have":[83],"been":[84],"implemented":[85],"validated":[87],"on":[88],"FPGA":[90],"board":[91],"CMOS":[94],"65":[95],"nm":[96],"technology.":[97]},"counts_by_year":[],"updated_date":"2026-03-28T08:17:26.163206","created_date":"2025-10-10T00:00:00"}