{"id":"https://openalex.org/W2124218270","doi":"https://doi.org/10.1109/ddecs.2009.5012135","title":"Logic synthesis method for pattern matching circuits implementation in FPGA with embedded memories","display_name":"Logic synthesis method for pattern matching circuits implementation in FPGA with embedded memories","publication_year":2009,"publication_date":"2009-01-01","ids":{"openalex":"https://openalex.org/W2124218270","doi":"https://doi.org/10.1109/ddecs.2009.5012135","mag":"2124218270"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2009.5012135","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2009.5012135","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5036301361","display_name":"Grzegorz Borowik","orcid":"https://orcid.org/0000-0003-4148-4817"},"institutions":[{"id":"https://openalex.org/I108403487","display_name":"Warsaw University of Technology","ror":"https://ror.org/00y0xnp53","country_code":"PL","type":"education","lineage":["https://openalex.org/I108403487"]},{"id":"https://openalex.org/I4210125529","display_name":"National Institute of Telecommunications","ror":"https://ror.org/03053v606","country_code":"PL","type":"facility","lineage":["https://openalex.org/I4210125529"]}],"countries":["PL"],"is_corresponding":true,"raw_author_name":"Grzegorz Borowik","raw_affiliation_strings":["Institute of Telecommunications, Warsaw University of Technology, Warsaw, Poland","Institute of Telecommunications, Warsaw University of Technology, Poland"],"affiliations":[{"raw_affiliation_string":"Institute of Telecommunications, Warsaw University of Technology, Warsaw, Poland","institution_ids":["https://openalex.org/I108403487"]},{"raw_affiliation_string":"Institute of Telecommunications, Warsaw University of Technology, Poland","institution_ids":["https://openalex.org/I4210125529","https://openalex.org/I108403487"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051919904","display_name":"Tadeusz \u0141uba","orcid":"https://orcid.org/0000-0002-4965-7842"},"institutions":[{"id":"https://openalex.org/I4210125529","display_name":"National Institute of Telecommunications","ror":"https://ror.org/03053v606","country_code":"PL","type":"facility","lineage":["https://openalex.org/I4210125529"]},{"id":"https://openalex.org/I108403487","display_name":"Warsaw University of Technology","ror":"https://ror.org/00y0xnp53","country_code":"PL","type":"education","lineage":["https://openalex.org/I108403487"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Tadeusz Luba","raw_affiliation_strings":["Institute of Telecommunications, Warsaw University of Technology, Warsaw, Poland","Institute of Telecommunications, Warsaw University of Technology, Poland"],"affiliations":[{"raw_affiliation_string":"Institute of Telecommunications, Warsaw University of Technology, Warsaw, Poland","institution_ids":["https://openalex.org/I108403487"]},{"raw_affiliation_string":"Institute of Telecommunications, Warsaw University of Technology, Poland","institution_ids":["https://openalex.org/I4210125529","https://openalex.org/I108403487"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5016478346","display_name":"B.J. Falkowski","orcid":null},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Bogdan J. Falkowski","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore","School of Electrical & Electronic Engineering , Nanyang Technological University , Singapore"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]},{"raw_affiliation_string":"School of Electrical & Electronic Engineering , Nanyang Technological University , Singapore","institution_ids":["https://openalex.org/I172675005"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5036301361"],"corresponding_institution_ids":["https://openalex.org/I108403487","https://openalex.org/I4210125529"],"apc_list":null,"apc_paid":null,"fwci":0.5276,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.68179576,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"54","issue":null,"first_page":"230","last_page":"233"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9944000244140625,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7670388221740723},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7442160248756409},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.7241597175598145},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.6908139586448669},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.638913631439209},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.6285309791564941},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.608259379863739},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.5795568227767944},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.5314587354660034},{"id":"https://openalex.org/keywords/matching","display_name":"Matching (statistics)","score":0.5211194157600403},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5111773610115051},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5002233982086182},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.49247345328330994},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.49076613783836365},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.47161439061164856},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.37375128269195557},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3721920847892761},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.36058229207992554},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3111802935600281},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.18190240859985352},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12419602274894714}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7670388221740723},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7442160248756409},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.7241597175598145},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.6908139586448669},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.638913631439209},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.6285309791564941},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.608259379863739},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.5795568227767944},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.5314587354660034},{"id":"https://openalex.org/C165064840","wikidata":"https://www.wikidata.org/wiki/Q1321061","display_name":"Matching (statistics)","level":2,"score":0.5211194157600403},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5111773610115051},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5002233982086182},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.49247345328330994},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.49076613783836365},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.47161439061164856},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.37375128269195557},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3721920847892761},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.36058229207992554},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3111802935600281},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.18190240859985352},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12419602274894714},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ddecs.2009.5012135","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2009.5012135","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4099999964237213,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W338455642","https://openalex.org/W1544620635","https://openalex.org/W1569514888","https://openalex.org/W1586713396","https://openalex.org/W1614476484","https://openalex.org/W1960511147","https://openalex.org/W1975889363","https://openalex.org/W2105761964","https://openalex.org/W2115025779","https://openalex.org/W2130471510","https://openalex.org/W2142269587","https://openalex.org/W3151501953","https://openalex.org/W6611545662","https://openalex.org/W6632451215","https://openalex.org/W6635108562"],"related_works":["https://openalex.org/W1939541994","https://openalex.org/W2994343469","https://openalex.org/W2102777336","https://openalex.org/W818963952","https://openalex.org/W2499931839","https://openalex.org/W2110968362","https://openalex.org/W4390345338","https://openalex.org/W4238178324","https://openalex.org/W3105918491","https://openalex.org/W1564891123"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,33,87],"new":[4],"cost-efficient":[5],"realization":[6],"scheme":[7],"of":[8,35,43,50,90,94],"pattern":[9],"matching":[10],"circuits":[11,31],"in":[12,64],"FPGA":[13],"structures":[14],"with":[15,78,86],"embedded":[16],"memory":[17],"blocks":[18,62],"(EMB).":[19],"The":[20,41],"general":[21],"idea":[22],"behind":[23],"the":[24,48,70,92],"proposed":[25,71],"method":[26,46,72,81],"is":[27],"to":[28],"implement":[29],"combinational":[30],"using":[32,55],"net":[34],"finite":[36],"state":[37],"machines":[38],"(FSM)":[39],"instead.":[40],"application":[42],"functional":[44],"decomposition":[45],"reduces":[47],"utilization":[49],"resources":[51],"by":[52,100],"implementing":[53],"FSMs":[54],"both":[56],"EMBs":[57],"and":[58],"LUT-based":[59],"programmable":[60],"logic":[61,95],"available":[63],"contemporary":[65],"FPGAs.":[66],"Experimental":[67],"results":[68],"for":[69],"are":[73],"also":[74],"shown.":[75],"A":[76],"comparison":[77],"another":[79],"dedicated":[80],"yields":[82],"extremely":[83],"encouraging":[84],"results:":[85],"comparable":[88],"number":[89,93],"EMBs,":[91],"cells":[96],"has":[97],"been":[98],"reduced":[99],"95%.":[101]},"counts_by_year":[{"year":2018,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":6},{"year":2014,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
