{"id":"https://openalex.org/W2112060085","doi":"https://doi.org/10.1109/ddecs.2009.5012101","title":"Asynchronous two-level logic of reduced cost","display_name":"Asynchronous two-level logic of reduced cost","publication_year":2009,"publication_date":"2009-01-01","ids":{"openalex":"https://openalex.org/W2112060085","doi":"https://doi.org/10.1109/ddecs.2009.5012101","mag":"2112060085"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2009.5012101","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2009.5012101","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5081940001","display_name":"Igor Lemberski","orcid":"https://orcid.org/0000-0001-9596-1506"},"institutions":[{"id":"https://openalex.org/I3132731249","display_name":"Baltic International Academy","ror":"https://ror.org/02r52cf76","country_code":"LV","type":"education","lineage":["https://openalex.org/I3132731249"]}],"countries":["LV"],"is_corresponding":true,"raw_author_name":"Igor Lemberski","raw_affiliation_strings":["Baltic International Academy, Riga, Latvia","Baltic International Academy Riga, Latvia"],"affiliations":[{"raw_affiliation_string":"Baltic International Academy, Riga, Latvia","institution_ids":["https://openalex.org/I3132731249"]},{"raw_affiliation_string":"Baltic International Academy Riga, Latvia","institution_ids":["https://openalex.org/I3132731249"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5023119816","display_name":"Petr Fi\u0161er","orcid":"https://orcid.org/0000-0001-5306-6343"},"institutions":[{"id":"https://openalex.org/I44504214","display_name":"Czech Technical University in Prague","ror":"https://ror.org/03kqpb082","country_code":"CZ","type":"education","lineage":["https://openalex.org/I44504214"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"Petr Fiser","raw_affiliation_strings":["Department of Computer Science & Engineering, Czech Technical University, Prague, Czech Republic","Department of Computer Science and Engineering, Czech Technical University in Prague, Czech Republic"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science & Engineering, Czech Technical University, Prague, Czech Republic","institution_ids":["https://openalex.org/I44504214"]},{"raw_affiliation_string":"Department of Computer Science and Engineering, Czech Technical University in Prague, Czech Republic","institution_ids":["https://openalex.org/I44504214"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5081940001"],"corresponding_institution_ids":["https://openalex.org/I3132731249"],"apc_list":null,"apc_paid":null,"fwci":0.3048,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.6436312,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"68","last_page":"73"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6987166404724121},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.6828988790512085},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.6604354381561279},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.6262826919555664},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.5677992105484009},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5472518801689148},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.48239290714263916},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.47776949405670166},{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.45924144983291626},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.4556657373905182},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.372997522354126},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.36814966797828674},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.20732828974723816},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.2033996880054474}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6987166404724121},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.6828988790512085},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.6604354381561279},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.6262826919555664},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.5677992105484009},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5472518801689148},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.48239290714263916},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.47776949405670166},{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.45924144983291626},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.4556657373905182},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.372997522354126},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.36814966797828674},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.20732828974723816},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2033996880054474},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.0},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/ddecs.2009.5012101","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2009.5012101","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.151.8950","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.151.8950","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://cs.felk.cvut.cz/~fiserp/papers/ddecs09.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.4699999988079071,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W336411274","https://openalex.org/W1484446818","https://openalex.org/W1498870363","https://openalex.org/W1514480347","https://openalex.org/W1544623790","https://openalex.org/W2015420475","https://openalex.org/W2030636464","https://openalex.org/W2033724727","https://openalex.org/W2104949917","https://openalex.org/W2105761964","https://openalex.org/W2107051475","https://openalex.org/W2129183345","https://openalex.org/W2137978379","https://openalex.org/W2143054129","https://openalex.org/W2145480542","https://openalex.org/W2147004330","https://openalex.org/W2167086449","https://openalex.org/W2288386471","https://openalex.org/W2487142227","https://openalex.org/W2911717499","https://openalex.org/W3146410802","https://openalex.org/W4242865834","https://openalex.org/W6696502059"],"related_works":["https://openalex.org/W3129977055","https://openalex.org/W1966764473","https://openalex.org/W1488117239","https://openalex.org/W2386022279","https://openalex.org/W2370649629","https://openalex.org/W659242671","https://openalex.org/W2356140560","https://openalex.org/W2051956260","https://openalex.org/W2356714888","https://openalex.org/W2770841929"],"abstract_inverted_index":{"We":[0,44,59],"propose":[1],"a":[2,7,19,34,55,83],"novel":[3],"synthesis":[4],"method":[5],"of":[6,12],"dual-rail":[8],"asynchronous":[9,66],"two-level":[10,67],"logic":[11,30,57],"reduced":[13],"cost.":[14],"It":[15],"is":[16,31],"based":[17],"on":[18],"model":[20],"that":[21,53],"operates":[22],"under":[23],"so":[24],"called":[25],"modified":[26],"weak":[27],"constraints.":[28],"The":[29,69],"implemented":[32],"as":[33],"minimized":[35],"AND-OR":[36],"structure,":[37],"together":[38],"with":[39,74],"the":[40,48,61,75],"completion":[41],"detection":[42],"logic.":[43,68],"formulated":[45],"and":[46,64],"proved":[47],"product":[49],"term":[50],"minimization":[51],"constraint":[52],"ensures":[54],"correct":[56],"behavior.":[58],"processed":[60],"MCNC":[62],"benchmarks":[63],"generated":[65],"implementation":[70],"complexity":[71],"was":[72],"compared":[73],"state-of-the-art":[76],"approach.":[77],"Using":[78],"our":[79],"approach,":[80],"we":[81],"achieved":[82],"significant":[84],"improvement.":[85]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":2}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
