{"id":"https://openalex.org/W2156240937","doi":"https://doi.org/10.1109/ddecs.2009.5012090","title":"Comparison of different test strategies on a mixed-signal circuit","display_name":"Comparison of different test strategies on a mixed-signal circuit","publication_year":2009,"publication_date":"2009-01-01","ids":{"openalex":"https://openalex.org/W2156240937","doi":"https://doi.org/10.1109/ddecs.2009.5012090","mag":"2156240937"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2009.5012090","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2009.5012090","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5018694023","display_name":"Juraj Brenku\u015d","orcid":null},"institutions":[{"id":"https://openalex.org/I110757952","display_name":"Slovak University of Technology in Bratislava","ror":"https://ror.org/0561ghm58","country_code":"SK","type":"education","lineage":["https://openalex.org/I110757952"]}],"countries":["SK"],"is_corresponding":true,"raw_author_name":"Juraj Brenkus","raw_affiliation_strings":["Department of Microelectronics, Slovak University of Technology, Bratislava, Slovakia"],"affiliations":[{"raw_affiliation_string":"Department of Microelectronics, Slovak University of Technology, Bratislava, Slovakia","institution_ids":["https://openalex.org/I110757952"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030204131","display_name":"Viera Stopjakov\u00e1","orcid":"https://orcid.org/0000-0002-0010-8965"},"institutions":[{"id":"https://openalex.org/I110757952","display_name":"Slovak University of Technology in Bratislava","ror":"https://ror.org/0561ghm58","country_code":"SK","type":"education","lineage":["https://openalex.org/I110757952"]}],"countries":["SK"],"is_corresponding":false,"raw_author_name":"Viera Stopjakova","raw_affiliation_strings":["Department of Microelectronics, Slovak University of Technology, Bratislava, Slovakia"],"affiliations":[{"raw_affiliation_string":"Department of Microelectronics, Slovak University of Technology, Bratislava, Slovakia","institution_ids":["https://openalex.org/I110757952"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062808173","display_name":"Ronny Vanhooren","orcid":null},"institutions":[{"id":"https://openalex.org/I4210110772","display_name":"ON Semiconductor (Belgium)","ror":"https://ror.org/0212gej90","country_code":"BE","type":"company","lineage":["https://openalex.org/I100625452","https://openalex.org/I4210110772"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Ronny Vanhooren","raw_affiliation_strings":["Test Methodology Team, ON Semiconductor, Oudenaarde, Belgium"],"affiliations":[{"raw_affiliation_string":"Test Methodology Team, ON Semiconductor, Oudenaarde, Belgium","institution_ids":["https://openalex.org/I4210110772"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5082035154","display_name":"Anton Chichkov","orcid":null},"institutions":[{"id":"https://openalex.org/I4210110772","display_name":"ON Semiconductor (Belgium)","ror":"https://ror.org/0212gej90","country_code":"BE","type":"company","lineage":["https://openalex.org/I100625452","https://openalex.org/I4210110772"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Anton Chichkov","raw_affiliation_strings":["Test Methodology Team, ON Semiconductor, Oudenaarde, Belgium"],"affiliations":[{"raw_affiliation_string":"Test Methodology Team, ON Semiconductor, Oudenaarde, Belgium","institution_ids":["https://openalex.org/I4210110772"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5018694023"],"corresponding_institution_ids":["https://openalex.org/I110757952"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.17326098,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"23","issue":null,"first_page":"16","last_page":"19"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9891999959945679,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9886999726295471,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/bridging","display_name":"Bridging (networking)","score":0.7857984304428101},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.6983515620231628},{"id":"https://openalex.org/keywords/parametric-statistics","display_name":"Parametric statistics","score":0.6492520570755005},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.6241915225982666},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6199628114700317},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.5503798723220825},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.4800663888454437},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.44741642475128174},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.4208933711051941},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.36088335514068604},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3400910496711731},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21442911028862},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.20431026816368103},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.18883532285690308},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1803426742553711},{"id":"https://openalex.org/keywords/statistics","display_name":"Statistics","score":0.12293976545333862},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.0892362892627716}],"concepts":[{"id":"https://openalex.org/C174348530","wikidata":"https://www.wikidata.org/wiki/Q188635","display_name":"Bridging (networking)","level":2,"score":0.7857984304428101},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.6983515620231628},{"id":"https://openalex.org/C117251300","wikidata":"https://www.wikidata.org/wiki/Q1849855","display_name":"Parametric statistics","level":2,"score":0.6492520570755005},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.6241915225982666},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6199628114700317},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.5503798723220825},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.4800663888454437},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.44741642475128174},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.4208933711051941},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.36088335514068604},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3400910496711731},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21442911028862},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.20431026816368103},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.18883532285690308},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1803426742553711},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.12293976545333862},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0892362892627716},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ddecs.2009.5012090","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2009.5012090","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1537352836","https://openalex.org/W1593860718","https://openalex.org/W1924227955","https://openalex.org/W2151509198","https://openalex.org/W3137483226","https://openalex.org/W4239282634","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W2091833418","https://openalex.org/W2021253405","https://openalex.org/W2913077774","https://openalex.org/W2145089576","https://openalex.org/W1986228509","https://openalex.org/W2147400189","https://openalex.org/W2340957901","https://openalex.org/W1991935474","https://openalex.org/W2786111245","https://openalex.org/W2148843359"],"abstract_inverted_index":{"An":[0],"experiment":[1],"comparing":[2],"the":[3,24,53],"efficiency":[4,49],"of":[5,26,52],"different":[6],"test":[7,21],"strategies":[8,22],"on":[9],"a":[10],"moderate":[11],"complexity":[12],"mixed-signal":[13],"circuit":[14],"with":[15],"1300":[16],"nodes":[17],"is":[18],"presented.":[19],"Selected":[20],"from":[23],"groups":[25],"functional,":[27],"structural":[28],"and":[29,40,50],"parametric":[30],"approaches":[31],"were":[32],"considered.":[33],"Bridging":[34],"faults":[35],"are":[36,44,55],"taken":[37],"into":[38],"account":[39],"fault":[41,47],"simulations":[42],"results":[43],"shown,":[45],"where":[46],"coverage,":[48],"quality":[51],"tests":[54],"evaluated.":[56]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
