{"id":"https://openalex.org/W3142313631","doi":"https://doi.org/10.1109/date.2010.5457234","title":"TLM+ modeling of embedded HW/SW systems","display_name":"TLM+ modeling of embedded HW/SW systems","publication_year":2010,"publication_date":"2010-03-01","ids":{"openalex":"https://openalex.org/W3142313631","doi":"https://doi.org/10.1109/date.2010.5457234","mag":"3142313631"},"language":"en","primary_location":{"id":"doi:10.1109/date.2010.5457234","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457234","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE 2010)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5046956677","display_name":"Wolfgang Ecker","orcid":"https://orcid.org/0000-0002-9362-8096"},"institutions":[{"id":"https://openalex.org/I137594350","display_name":"Infineon Technologies (Germany)","ror":"https://ror.org/005kw6t15","country_code":"DE","type":"company","lineage":["https://openalex.org/I137594350"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Wolfgang Ecker","raw_affiliation_strings":["Infineon Technologies, Neubiberg, Germany"],"affiliations":[{"raw_affiliation_string":"Infineon Technologies, Neubiberg, Germany","institution_ids":["https://openalex.org/I137594350"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040173035","display_name":"Volkan Esen","orcid":null},"institutions":[{"id":"https://openalex.org/I137594350","display_name":"Infineon Technologies (Germany)","ror":"https://ror.org/005kw6t15","country_code":"DE","type":"company","lineage":["https://openalex.org/I137594350"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Volkan Esen","raw_affiliation_strings":["Infineon Technologies, Germany"],"affiliations":[{"raw_affiliation_string":"Infineon Technologies, Germany","institution_ids":["https://openalex.org/I137594350"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004313244","display_name":"R. Schwencker","orcid":null},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Robert Schwencker","raw_affiliation_strings":["Technical University of M\u00fcnchen, Germany"],"affiliations":[{"raw_affiliation_string":"Technical University of M\u00fcnchen, Germany","institution_ids":["https://openalex.org/I62916508"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065997452","display_name":"Thomas Steininger","orcid":null},"institutions":[{"id":"https://openalex.org/I137594350","display_name":"Infineon Technologies (Germany)","ror":"https://ror.org/005kw6t15","country_code":"DE","type":"company","lineage":["https://openalex.org/I137594350"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Thomas Steininger","raw_affiliation_strings":["Infineon Technologies, Germany"],"affiliations":[{"raw_affiliation_string":"Infineon Technologies, Germany","institution_ids":["https://openalex.org/I137594350"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5062218687","display_name":"Michael Velten","orcid":null},"institutions":[{"id":"https://openalex.org/I137594350","display_name":"Infineon Technologies (Germany)","ror":"https://ror.org/005kw6t15","country_code":"DE","type":"company","lineage":["https://openalex.org/I137594350"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Michael Velten","raw_affiliation_strings":["Infineon Technologies, Germany"],"affiliations":[{"raw_affiliation_string":"Infineon Technologies, Germany","institution_ids":["https://openalex.org/I137594350"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5046956677"],"corresponding_institution_ids":["https://openalex.org/I137594350"],"apc_list":null,"apc_paid":null,"fwci":2.1367,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.88905895,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"75","last_page":"80"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8248366117477417},{"id":"https://openalex.org/keywords/transaction-level-modeling","display_name":"Transaction-level modeling","score":0.7152602672576904},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.6523536443710327},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.6038572192192078},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5548748970031738},{"id":"https://openalex.org/keywords/database-transaction","display_name":"Database transaction","score":0.5219590067863464},{"id":"https://openalex.org/keywords/abstraction-layer","display_name":"Abstraction layer","score":0.4560454189777374},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.43817609548568726},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4297095537185669},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.4296317398548126},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.41654375195503235},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.40683022141456604},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.18659579753875732},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.12402915954589844}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8248366117477417},{"id":"https://openalex.org/C169571997","wikidata":"https://www.wikidata.org/wiki/Q966099","display_name":"Transaction-level modeling","level":3,"score":0.7152602672576904},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.6523536443710327},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.6038572192192078},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5548748970031738},{"id":"https://openalex.org/C75949130","wikidata":"https://www.wikidata.org/wiki/Q848010","display_name":"Database transaction","level":2,"score":0.5219590067863464},{"id":"https://openalex.org/C147358964","wikidata":"https://www.wikidata.org/wiki/Q1200992","display_name":"Abstraction layer","level":3,"score":0.4560454189777374},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.43817609548568726},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4297095537185669},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.4296317398548126},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.41654375195503235},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.40683022141456604},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.18659579753875732},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.12402915954589844},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2010.5457234","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457234","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE 2010)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W1525398417","https://openalex.org/W2149449165","https://openalex.org/W2112223413","https://openalex.org/W2119788505","https://openalex.org/W4245833509","https://openalex.org/W1901380330","https://openalex.org/W2123581614","https://openalex.org/W1831349210","https://openalex.org/W2552808814","https://openalex.org/W1486803855"],"abstract_inverted_index":{"Virtual":[0],"Prototypes":[1],"(VPs)":[2],"based":[3],"on":[4],"Transaction":[5],"Level":[6],"Modeling":[7],"(TLM)":[8],"have":[9],"become":[10,35],"a":[11,36,64,73,126,148,155],"de-facto":[12],"standard":[13],"in":[14],"today's":[15],"SoC":[16,29],"design,":[17],"enabling":[18],"early":[19],"SW":[20,114],"development.":[21],"However,":[22],"due":[23],"to":[24,45,68,99,112,118,122,152],"the":[25,55,84,88,106,110,120,135],"growing":[26],"complexity":[27],"of":[28,93,137,150,158],"architectures":[30],"full":[31],"system":[32],"simulations":[33],"(HW+SW)":[34],"bottleneck":[37],"reducing":[38],"this":[39],"benefit.":[40],"Hence,":[41],"it":[42],"is":[43,131],"necessary":[44],"develop":[46],"modeling":[47,65,75],"styles":[48],"which":[49,133],"allow":[50],"for":[51],"further":[52],"abstraction":[53,76],"beyond":[54],"currently":[56],"applied":[57],"TLM":[58],"methodology.":[59],"This":[60],"paper":[61],"introduces":[62],"such":[63],"style,":[66],"referred":[67],"as":[69],"TLM+.":[70],"It":[71],"enables":[72],"higher":[74],"through":[77],"merging":[78,142],"hardware":[79],"dependent":[80],"driver":[81],"software":[82],"at":[83,154],"lowest":[85],"level":[86],"with":[87],"HW":[89,94,107,143],"interface.":[90],"Thus,":[91],"sequences":[92],"transactions":[95,102],"can":[96],"be":[97],"merged":[98],"single":[100],"HW/SW":[101],"while":[103],"preserving":[104],"both":[105],"architecture":[108],"and":[109],"low-level":[111],"high-level":[113],"interfaces.":[115],"In":[116],"order":[117],"maintain":[119],"ability":[121],"validate":[123],"timing-critical":[124],"paths,":[125],"new":[127],"resource":[128],"model":[129],"concept":[130],"introduced":[132],"compensates":[134],"loss":[136],"timing":[138,156],"information,":[139],"induced":[140],"by":[141],"transactions.":[144],"Experimental":[145],"results":[146],"show":[147],"speed-up":[149],"up":[151],"1000x":[153],"error":[157],"approximately":[159],"10%.":[160]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
