{"id":"https://openalex.org/W3143919365","doi":"https://doi.org/10.1109/date.2010.5457171","title":"A reconfigurable hardware for one bit transform based multiple reference frame Motion Estimation","display_name":"A reconfigurable hardware for one bit transform based multiple reference frame Motion Estimation","publication_year":2010,"publication_date":"2010-03-01","ids":{"openalex":"https://openalex.org/W3143919365","doi":"https://doi.org/10.1109/date.2010.5457171","mag":"3143919365"},"language":"en","primary_location":{"id":"doi:10.1109/date.2010.5457171","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457171","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006895297","display_name":"Ata Ak\u0131n","orcid":"https://orcid.org/0000-0002-1773-0857"},"institutions":[{"id":"https://openalex.org/I134235054","display_name":"Sabanc\u0131 \u00dcniversitesi","ror":"https://ror.org/049asqa32","country_code":"TR","type":"education","lineage":["https://openalex.org/I134235054"]}],"countries":["TR"],"is_corresponding":true,"raw_author_name":"A Akin","raw_affiliation_strings":["Faculty of Engineering and Natural Sciences, Sabanci University, Istanbul, Turkey"],"affiliations":[{"raw_affiliation_string":"Faculty of Engineering and Natural Sciences, Sabanci University, Istanbul, Turkey","institution_ids":["https://openalex.org/I134235054"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060381631","display_name":"Gokhan Sayilar","orcid":null},"institutions":[{"id":"https://openalex.org/I134235054","display_name":"Sabanc\u0131 \u00dcniversitesi","ror":"https://ror.org/049asqa32","country_code":"TR","type":"education","lineage":["https://openalex.org/I134235054"]}],"countries":["TR"],"is_corresponding":false,"raw_author_name":"G Sayilar","raw_affiliation_strings":["Faculty of Engineering and Natural Sciences, Sabanci University, Istanbul, Turkey"],"affiliations":[{"raw_affiliation_string":"Faculty of Engineering and Natural Sciences, Sabanci University, Istanbul, Turkey","institution_ids":["https://openalex.org/I134235054"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018819924","display_name":"\u0130lker Hamzao\u011flu","orcid":"https://orcid.org/0000-0002-6491-689X"},"institutions":[{"id":"https://openalex.org/I134235054","display_name":"Sabanc\u0131 \u00dcniversitesi","ror":"https://ror.org/049asqa32","country_code":"TR","type":"education","lineage":["https://openalex.org/I134235054"]}],"countries":["TR"],"is_corresponding":false,"raw_author_name":"I Hamzaoglu","raw_affiliation_strings":["Faculty of Engineering and Natural Sciences, Sabanci University, Istanbul, Turkey"],"affiliations":[{"raw_affiliation_string":"Faculty of Engineering and Natural Sciences, Sabanci University, Istanbul, Turkey","institution_ids":["https://openalex.org/I134235054"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5006895297"],"corresponding_institution_ids":["https://openalex.org/I134235054"],"apc_list":null,"apc_paid":null,"fwci":1.0115,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.78616352,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"393","last_page":"398"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10531","display_name":"Advanced Vision and Imaging","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8191535472869873},{"id":"https://openalex.org/keywords/reconfigurability","display_name":"Reconfigurability","score":0.7770116329193115},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6872225999832153},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.6851968169212341},{"id":"https://openalex.org/keywords/motion-estimation","display_name":"Motion estimation","score":0.6620656251907349},{"id":"https://openalex.org/keywords/reference-frame","display_name":"Reference frame","score":0.6062589883804321},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5769822001457214},{"id":"https://openalex.org/keywords/computational-complexity-theory","display_name":"Computational complexity theory","score":0.5361272096633911},{"id":"https://openalex.org/keywords/frame","display_name":"Frame (networking)","score":0.5360524654388428},{"id":"https://openalex.org/keywords/hardware-architecture","display_name":"Hardware architecture","score":0.5055797100067139},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.43938836455345154},{"id":"https://openalex.org/keywords/data-compression","display_name":"Data compression","score":0.4186231195926666},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3306058645248413},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.2284144163131714},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.18448036909103394},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.09136417508125305}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8191535472869873},{"id":"https://openalex.org/C2780149590","wikidata":"https://www.wikidata.org/wiki/Q7302742","display_name":"Reconfigurability","level":2,"score":0.7770116329193115},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6872225999832153},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.6851968169212341},{"id":"https://openalex.org/C10161872","wikidata":"https://www.wikidata.org/wiki/Q557891","display_name":"Motion estimation","level":2,"score":0.6620656251907349},{"id":"https://openalex.org/C172849965","wikidata":"https://www.wikidata.org/wiki/Q3148875","display_name":"Reference frame","level":3,"score":0.6062589883804321},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5769822001457214},{"id":"https://openalex.org/C179799912","wikidata":"https://www.wikidata.org/wiki/Q205084","display_name":"Computational complexity theory","level":2,"score":0.5361272096633911},{"id":"https://openalex.org/C126042441","wikidata":"https://www.wikidata.org/wiki/Q1324888","display_name":"Frame (networking)","level":2,"score":0.5360524654388428},{"id":"https://openalex.org/C65232700","wikidata":"https://www.wikidata.org/wiki/Q5656403","display_name":"Hardware architecture","level":3,"score":0.5055797100067139},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.43938836455345154},{"id":"https://openalex.org/C78548338","wikidata":"https://www.wikidata.org/wiki/Q2493","display_name":"Data compression","level":2,"score":0.4186231195926666},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3306058645248413},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.2284144163131714},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.18448036909103394},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.09136417508125305},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2010.5457171","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457171","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1965273945","https://openalex.org/W1984814279","https://openalex.org/W1986477787","https://openalex.org/W2039181402","https://openalex.org/W2087386508","https://openalex.org/W2099124466","https://openalex.org/W2106914334","https://openalex.org/W2110020242","https://openalex.org/W2114021467","https://openalex.org/W2114961653","https://openalex.org/W2142251731","https://openalex.org/W2143935035","https://openalex.org/W2488097972","https://openalex.org/W3146124357"],"related_works":["https://openalex.org/W3103981520","https://openalex.org/W200972441","https://openalex.org/W2038220260","https://openalex.org/W1545578515","https://openalex.org/W1857140530","https://openalex.org/W2150194641","https://openalex.org/W1544665014","https://openalex.org/W2098458348","https://openalex.org/W2158008050","https://openalex.org/W3166559827"],"abstract_inverted_index":{"Motion":[0],"Estimation":[1],"(ME)":[2],"is":[3,68,83,111,141,171],"the":[4,71,78,94,98,107,116,125,153,167],"most":[5],"computationally":[6],"intensive":[7],"part":[8],"of":[9,39,85,100,106,120,152,173],"video":[10,13],"compression":[11],"and":[12,59,118,134,170],"enhancement":[14],"systems.":[15],"One":[16],"bit":[17],"transform":[18],"(1BT)":[19],"based":[20,41,73,123],"ME":[21,49,55,74,92,95,109,132,148],"algorithms":[22],"have":[23],"low":[24],"computational":[25,102,135],"complexity.":[26,103,136],"Therefore,":[27],"in":[28,63,77,87,128,143,155,166],"this":[29],"paper,":[30],"we":[31],"propose":[32],"a":[33,156],"high":[34],"performance":[35,96,133],"reconfigurable":[36],"hardware":[37,50,67,75,110,139,149],"architecture":[38,51,140],"1BT":[40,72],"multiple":[42],"reference":[43,61,89,121],"frame":[44],"(MRF)":[45],"ME.":[46],"The":[47,65,104,137,146],"proposed":[48,66,108,138],"performs":[52],"full":[53,179],"search":[54],"for":[56],"4":[57,60,88],"Macroblocks":[58],"frames":[62,122,182],"parallel.":[64],"faster":[69],"than":[70],"reported":[76],"literature":[79],"even":[80],"though":[81],"it":[82],"capable":[84,172],"searching":[86],"frames.":[90],"MRF":[91,147],"increases":[93],"at":[97,163],"expense":[99],"increased":[101],"reconfigurability":[105],"used":[112],"to":[113,130],"statically":[114],"configure":[115],"number":[117],"selection":[119],"on":[124],"application":[126],"requirements":[127],"order":[129],"trade-off":[131],"implemented":[142],"Verilog":[144],"HDL.":[145],"consumes":[150],"%65":[151],"slices":[154],"Xilinx":[157],"XC2VP30-7":[158],"FPGA.":[159],"It":[160],"can":[161],"work":[162],"191":[164],"MHz":[165],"same":[168],"FPGA":[169],"processing":[174],"83":[175],"1920":[176],"\u00d7":[177],"1080":[178],"High":[180],"Definition":[181],"per":[183],"second.":[184]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}