{"id":"https://openalex.org/W4242246193","doi":"https://doi.org/10.1109/date.2010.5457113","title":"A methodology for the characterization of process variation in NoC links","display_name":"A methodology for the characterization of process variation in NoC links","publication_year":2010,"publication_date":"2010-03-01","ids":{"openalex":"https://openalex.org/W4242246193","doi":"https://doi.org/10.1109/date.2010.5457113"},"language":"en","primary_location":{"id":"doi:10.1109/date.2010.5457113","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457113","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047492364","display_name":"Carles Hern\u00e1ndez","orcid":"https://orcid.org/0000-0001-5393-3195"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"Carles Hernandez","raw_affiliation_strings":["Grupo de Architecturas Paralelas, Departamento de Inform\u00e1tica de Sistemas, Universidad Polit\u00e9cnica de Valencia, Valencia, Spain"],"affiliations":[{"raw_affiliation_string":"Grupo de Architecturas Paralelas, Departamento de Inform\u00e1tica de Sistemas, Universidad Polit\u00e9cnica de Valencia, Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050691850","display_name":"Federico Silla","orcid":"https://orcid.org/0000-0002-6435-1200"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Federico Silla","raw_affiliation_strings":["Grupo de Architecturas Paralelas, Departamento de Inform\u00e1tica de Sistemas, Universidad Polit\u00e9cnica de Valencia, Valencia, Spain"],"affiliations":[{"raw_affiliation_string":"Grupo de Architecturas Paralelas, Departamento de Inform\u00e1tica de Sistemas, Universidad Polit\u00e9cnica de Valencia, Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040384183","display_name":"J. Duato","orcid":"https://orcid.org/0000-0002-7785-0607"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Jose Duato","raw_affiliation_strings":["Grupo de Architecturas Paralelas, Departamento de Inform\u00e1tica de Sistemas, Universidad Polit\u00e9cnica de Valencia, Valencia, Spain"],"affiliations":[{"raw_affiliation_string":"Grupo de Architecturas Paralelas, Departamento de Inform\u00e1tica de Sistemas, Universidad Polit\u00e9cnica de Valencia, Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5047492364"],"corresponding_institution_ids":["https://openalex.org/I60053951"],"apc_list":null,"apc_paid":null,"fwci":5.6979,"has_fulltext":false,"cited_by_count":24,"citation_normalized_percentile":{"value":0.96488108,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"685","last_page":"690"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.7735924124717712},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.6583331823348999},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6469073295593262},{"id":"https://openalex.org/keywords/variation","display_name":"Variation (astronomy)","score":0.6341066360473633},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.6321249008178711},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.6293724775314331},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.614957332611084},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5308844447135925},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.46498483419418335},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4315243065357208},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3533307909965515},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.345615416765213},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1380627155303955},{"id":"https://openalex.org/keywords/geology","display_name":"Geology","score":0.0698499083518982},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.06556162238121033}],"concepts":[{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.7735924124717712},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.6583331823348999},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6469073295593262},{"id":"https://openalex.org/C2778334786","wikidata":"https://www.wikidata.org/wiki/Q1586270","display_name":"Variation (astronomy)","level":2,"score":0.6341066360473633},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.6321249008178711},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.6293724775314331},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.614957332611084},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5308844447135925},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.46498483419418335},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4315243065357208},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3533307909965515},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.345615416765213},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1380627155303955},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0698499083518982},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.06556162238121033},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C44870925","wikidata":"https://www.wikidata.org/wiki/Q37547","display_name":"Astrophysics","level":1,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2010.5457113","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457113","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W153999141","https://openalex.org/W1693570377","https://openalex.org/W2118015263","https://openalex.org/W2127341531","https://openalex.org/W2128433628","https://openalex.org/W2129883611","https://openalex.org/W2130861573","https://openalex.org/W2143555564","https://openalex.org/W2150283124","https://openalex.org/W2159856958","https://openalex.org/W2162354220","https://openalex.org/W2166925534","https://openalex.org/W3140261852","https://openalex.org/W3145747011","https://openalex.org/W3147018723","https://openalex.org/W4234308027","https://openalex.org/W4244034697","https://openalex.org/W6606197985","https://openalex.org/W6678856879","https://openalex.org/W6679287675","https://openalex.org/W6683275698","https://openalex.org/W6825616103"],"related_works":["https://openalex.org/W2135981148","https://openalex.org/W2065289416","https://openalex.org/W2148989037","https://openalex.org/W2388672758","https://openalex.org/W2141405780","https://openalex.org/W2754086592","https://openalex.org/W2144357574","https://openalex.org/W2017236304","https://openalex.org/W4230458348","https://openalex.org/W3198758847"],"abstract_inverted_index":{"Associated":[0],"with":[1],"the":[2,8,14,21,77],"ever":[3],"growing":[4],"integration":[5],"scales":[6],"is":[7],"increase":[9],"in":[10,35,50],"process":[11],"variability.":[12],"In":[13,39],"context":[15],"of":[16],"network-on-chip,":[17],"this":[18,40],"variability":[19,73],"affects":[20],"maximum":[22],"frequency":[23],"that":[24,31,70],"could":[25],"be":[26],"sustained":[27],"by":[28],"each":[29],"link":[30],"interconnects":[32],"two":[33],"cores":[34],"a":[36,44],"chip":[37],"multiprocessor.":[38],"paper":[41],"we":[42],"present":[43],"methodology":[45],"to":[46,58],"model":[47],"delay":[48],"variations":[49],"NoC":[51],"links.":[52],"We":[53],"also":[54],"show":[55,69],"its":[56],"application":[57],"several":[59],"technologies,":[60],"namely":[61],"45nm,":[62],"32nm,":[63],"22nm,":[64],"and":[65],"16nm.":[66],"Simulation":[67],"results":[68],"conclusions":[71],"about":[72],"greatly":[74],"depend":[75],"on":[76],"implementation":[78],"context.":[79]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":6}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}