{"id":"https://openalex.org/W3149674220","doi":"https://doi.org/10.1109/date.2010.5457089","title":"Formal specification of networks-on-chips: deadlock and evacuation","display_name":"Formal specification of networks-on-chips: deadlock and evacuation","publication_year":2010,"publication_date":"2010-03-01","ids":{"openalex":"https://openalex.org/W3149674220","doi":"https://doi.org/10.1109/date.2010.5457089","mag":"3149674220"},"language":"en","primary_location":{"id":"doi:10.1109/date.2010.5457089","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457089","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067135306","display_name":"Freek Verbeek","orcid":"https://orcid.org/0000-0002-6625-1123"},"institutions":[{"id":"https://openalex.org/I7876267","display_name":"Open University of the Netherlands","ror":"https://ror.org/018dfmf50","country_code":"NL","type":"education","lineage":["https://openalex.org/I7876267"]},{"id":"https://openalex.org/I145872427","display_name":"Radboud University Nijmegen","ror":"https://ror.org/016xsfp80","country_code":"NL","type":"education","lineage":["https://openalex.org/I145872427"]}],"countries":["NL"],"is_corresponding":true,"raw_author_name":"Freek Verbeek","raw_affiliation_strings":["Institute of Computing and Information Sciences, Radboud University Nijmegen, Netherlands","School of Computer Science, Open University, Netherlands, Netherlands"],"affiliations":[{"raw_affiliation_string":"Institute of Computing and Information Sciences, Radboud University Nijmegen, Netherlands","institution_ids":["https://openalex.org/I145872427"]},{"raw_affiliation_string":"School of Computer Science, Open University, Netherlands, Netherlands","institution_ids":["https://openalex.org/I7876267"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5088595514","display_name":"Julien Schmaltz","orcid":null},"institutions":[{"id":"https://openalex.org/I7876267","display_name":"Open University of the Netherlands","ror":"https://ror.org/018dfmf50","country_code":"NL","type":"education","lineage":["https://openalex.org/I7876267"]},{"id":"https://openalex.org/I145872427","display_name":"Radboud University Nijmegen","ror":"https://ror.org/016xsfp80","country_code":"NL","type":"education","lineage":["https://openalex.org/I145872427"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Julien Schmaltz","raw_affiliation_strings":["Institute of Computing and Information Sciences, Radboud University Nijmegen, Netherlands","School of Computer Science, Open University, Netherlands, Netherlands"],"affiliations":[{"raw_affiliation_string":"Institute of Computing and Information Sciences, Radboud University Nijmegen, Netherlands","institution_ids":["https://openalex.org/I145872427"]},{"raw_affiliation_string":"School of Computer Science, Open University, Netherlands, Netherlands","institution_ids":["https://openalex.org/I7876267"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5067135306"],"corresponding_institution_ids":["https://openalex.org/I145872427","https://openalex.org/I7876267"],"apc_list":null,"apc_paid":null,"fwci":2.5179,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.90459067,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"3725 2005","issue":null,"first_page":"1701","last_page":"1706"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/liveness","display_name":"Liveness","score":0.8308656215667725},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7773252725601196},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.7554050087928772},{"id":"https://openalex.org/keywords/deadlock","display_name":"Deadlock","score":0.7200509905815125},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6031493544578552},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.5787983536720276},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5495381355285645},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.5416264533996582},{"id":"https://openalex.org/keywords/deadlock-prevention-algorithms","display_name":"Deadlock prevention algorithms","score":0.5370276570320129},{"id":"https://openalex.org/keywords/parametric-statistics","display_name":"Parametric statistics","score":0.48239338397979736},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.47680923342704773},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4730726182460785},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.44982782006263733},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.29490047693252563},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.14913615584373474}],"concepts":[{"id":"https://openalex.org/C15569618","wikidata":"https://www.wikidata.org/wiki/Q3561421","display_name":"Liveness","level":2,"score":0.8308656215667725},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7773252725601196},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.7554050087928772},{"id":"https://openalex.org/C159023740","wikidata":"https://www.wikidata.org/wiki/Q623276","display_name":"Deadlock","level":2,"score":0.7200509905815125},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6031493544578552},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.5787983536720276},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5495381355285645},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.5416264533996582},{"id":"https://openalex.org/C113429609","wikidata":"https://www.wikidata.org/wiki/Q4060699","display_name":"Deadlock prevention algorithms","level":3,"score":0.5370276570320129},{"id":"https://openalex.org/C117251300","wikidata":"https://www.wikidata.org/wiki/Q1849855","display_name":"Parametric statistics","level":2,"score":0.48239338397979736},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.47680923342704773},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4730726182460785},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44982782006263733},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.29490047693252563},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.14913615584373474},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/date.2010.5457089","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457089","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","raw_type":"proceedings-article"},{"id":"pmh:oai:repository.ubn.ru.nl:2066/83494","is_oa":false,"landing_page_url":"http://hdl.handle.net/2066/83494","pdf_url":null,"source":{"id":"https://openalex.org/S4306401067","display_name":"Radboud Repository (Radboud University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I145872427","host_organization_name":"Radboud University Nijmegen","host_organization_lineage":["https://openalex.org/I145872427"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Preas, K. (ed.), DATE 2010: Design, Automation and Test in Europe Conference and Exhibition, 8-12 March, Dresden, Germany, 2010. Proceedings, pp. 1701-1706","raw_type":"Article in monograph or in proceedings"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6299999952316284,"id":"https://metadata.un.org/sdg/11","display_name":"Sustainable cities and communities"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321800","display_name":"Nederlandse Organisatie voor Wetenschappelijk Onderzoek","ror":"https://ror.org/04jsz6e67"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1542895703","https://openalex.org/W1982246372","https://openalex.org/W1992091351","https://openalex.org/W2030397744","https://openalex.org/W2056997919","https://openalex.org/W2067885187","https://openalex.org/W2081911632","https://openalex.org/W2106130641","https://openalex.org/W2123184444","https://openalex.org/W2124552466","https://openalex.org/W2126261264","https://openalex.org/W2128939182","https://openalex.org/W2152099665","https://openalex.org/W2154323564","https://openalex.org/W2159122053","https://openalex.org/W2160642395","https://openalex.org/W2752885492","https://openalex.org/W4254738219"],"related_works":["https://openalex.org/W2050076411","https://openalex.org/W4226119751","https://openalex.org/W2001478969","https://openalex.org/W1542183432","https://openalex.org/W2360686363","https://openalex.org/W1900787600","https://openalex.org/W2136552483","https://openalex.org/W2166954426","https://openalex.org/W1867637656","https://openalex.org/W2329232208"],"abstract_inverted_index":{"Networks-on-chips":[0],"(NoC)":[1],"are":[2],"emerging":[3],"as":[4],"a":[5,15,48],"promising":[6],"interconnect":[7],"solution":[8],"for":[9,47],"efficient":[10],"Multi-Processors":[11],"Systems-on-Chips.":[12],"We":[13,24],"propose":[14],"methodology":[16],"that":[17,28],"supports":[18],"the":[19,37,53],"specification":[20],"of":[21,36],"parametric":[22,49],"NoCs.":[23],"provide":[25],"sufficient":[26],"constraints":[27,46],"ensure":[29],"deadlock-free":[30],"routing,":[31],"functional":[32],"correctness,":[33],"and":[34],"liveness":[35],"design.":[38],"To":[39],"illustrate":[40],"our":[41],"method,":[42],"we":[43],"discharge":[44],"these":[45],"NoC":[50],"inspired":[51],"by":[52],"HERMES":[54],"architecture.":[55]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}