{"id":"https://openalex.org/W3145937681","doi":"https://doi.org/10.1109/date.2010.5457050","title":"Checking and deriving module paths in Verilog cell library descriptions","display_name":"Checking and deriving module paths in Verilog cell library descriptions","publication_year":2010,"publication_date":"2010-03-01","ids":{"openalex":"https://openalex.org/W3145937681","doi":"https://doi.org/10.1109/date.2010.5457050","mag":"3145937681"},"language":"en","primary_location":{"id":"doi:10.1109/date.2010.5457050","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457050","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE 2010)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5022191963","display_name":"Matthias Raffelsieper","orcid":null},"institutions":[{"id":"https://openalex.org/I83019370","display_name":"Eindhoven University of Technology","ror":"https://ror.org/02c2kyt77","country_code":"NL","type":"education","lineage":["https://openalex.org/I83019370"]}],"countries":["NL"],"is_corresponding":true,"raw_author_name":"Matthias Raffelsieper","raw_affiliation_strings":["CS Department, University\uc2a0of\uc2a0Technology Eindhoven, Eindhoven, Netherlands"],"affiliations":[{"raw_affiliation_string":"CS Department, University\uc2a0of\uc2a0Technology Eindhoven, Eindhoven, Netherlands","institution_ids":["https://openalex.org/I83019370"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101493818","display_name":"Mohammad Reza Mousavi","orcid":"https://orcid.org/0000-0002-4869-6794"},"institutions":[{"id":"https://openalex.org/I83019370","display_name":"Eindhoven University of Technology","ror":"https://ror.org/02c2kyt77","country_code":"NL","type":"education","lineage":["https://openalex.org/I83019370"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"MohammadReza Mousavi","raw_affiliation_strings":["CS Department, University\uc2a0of\uc2a0Technology Eindhoven, Eindhoven, Netherlands"],"affiliations":[{"raw_affiliation_string":"CS Department, University\uc2a0of\uc2a0Technology Eindhoven, Eindhoven, Netherlands","institution_ids":["https://openalex.org/I83019370"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5060455436","display_name":"Chris Strolenberg","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Chris Strolenberg","raw_affiliation_strings":["Fenix, Eindhoven, Netherlands"],"affiliations":[{"raw_affiliation_string":"Fenix, Eindhoven, Netherlands","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5022191963"],"corresponding_institution_ids":["https://openalex.org/I83019370"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.36677267,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1506","last_page":"1511"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.836184561252594},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.8163629174232483},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.6270337104797363},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.5954941511154175},{"id":"https://openalex.org/keywords/event","display_name":"Event (particle physics)","score":0.5184261798858643},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.4545646011829376},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.41822999715805054},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3404654860496521},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.32291078567504883},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.27003559470176697},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.10898205637931824},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.09274929761886597},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07231664657592773}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.836184561252594},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.8163629174232483},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.6270337104797363},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.5954941511154175},{"id":"https://openalex.org/C2779662365","wikidata":"https://www.wikidata.org/wiki/Q5416694","display_name":"Event (particle physics)","level":2,"score":0.5184261798858643},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.4545646011829376},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.41822999715805054},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3404654860496521},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.32291078567504883},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.27003559470176697},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.10898205637931824},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.09274929761886597},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07231664657592773},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C187736073","wikidata":"https://www.wikidata.org/wiki/Q2920921","display_name":"Management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2010.5457050","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457050","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE 2010)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1982765126","https://openalex.org/W2010065567","https://openalex.org/W2051804316","https://openalex.org/W2103059126","https://openalex.org/W2127920376","https://openalex.org/W2134028345","https://openalex.org/W2155643415","https://openalex.org/W6680139559"],"related_works":["https://openalex.org/W1761969858","https://openalex.org/W2371211312","https://openalex.org/W2391470376","https://openalex.org/W2118330589","https://openalex.org/W2159551383","https://openalex.org/W2471362132","https://openalex.org/W2117342402","https://openalex.org/W2387139896","https://openalex.org/W2388558414","https://openalex.org/W2604877941"],"abstract_inverted_index":{"Module":[0],"paths":[1,33,68,101,119],"are":[2,102],"often":[3],"used":[4],"to":[5,28,95,116],"specify":[6,62],"the":[7,19,55,78,86,98,105],"delays":[8],"of":[9,77,124],"cells":[10],"in":[11,54,73,104],"a":[12,40,46,93,114,121,125],"Verilog":[13],"cell":[14],"library":[15],"description,":[16],"which":[17,49],"define":[18],"propagation":[20],"delay":[21],"for":[22],"an":[23,26,29,36],"event":[24],"from":[25,120],"input":[27],"output.":[30],"Specifying":[31],"such":[32],"manually":[34],"is":[35,43],"error":[37],"prone":[38],"task;":[39],"forgotten":[41],"path":[42],"interpreted":[44],"as":[45],"zero":[47],"delay,":[48],"can":[50,61,70],"cause":[51],"further":[52],"flaws":[53],"subsequent":[56,87],"design":[57,88],"steps.":[58],"Moreover,":[59],"one":[60],"superfluous":[63],"module":[64,67,100,118],"paths,":[65],"i.e.,":[66],"that":[69],"never":[71],"occur":[72],"any":[74],"practical":[75],"run":[76],"model":[79],"and":[80],"hence,":[81],"make":[82],"excessive":[83],"restrictions":[84],"on":[85],"decision.":[89],"This":[90],"paper":[91],"presents":[92],"method":[94,115],"check":[96],"whether":[97],"given":[99],"reflected":[103],"functional":[106,122],"implementation.":[107],"Complementing":[108],"this":[109],"check,":[110],"we":[111],"also":[112],"present":[113],"derive":[117],"description":[123],"cell.":[126]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
