{"id":"https://openalex.org/W4234341242","doi":"https://doi.org/10.1109/date.2010.5457005","title":"Exploiting local logic structures to optimize multi-core SoC floorplanning","display_name":"Exploiting local logic structures to optimize multi-core SoC floorplanning","publication_year":2010,"publication_date":"2010-03-01","ids":{"openalex":"https://openalex.org/W4234341242","doi":"https://doi.org/10.1109/date.2010.5457005"},"language":"en","primary_location":{"id":"doi:10.1109/date.2010.5457005","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457005","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref","datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://doi.org/10.7916/d8b85g0k","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5003710372","display_name":"Chenghong Li","orcid":"https://orcid.org/0009-0004-0604-7421"},"institutions":[{"id":"https://openalex.org/I78577930","display_name":"Columbia University","ror":"https://ror.org/00hj8s172","country_code":"US","type":"education","lineage":["https://openalex.org/I78577930"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Cheng-Hong Li","raw_affiliation_strings":["Department of Computer Science, Columbia University, New York, NY, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Columbia University, New York, NY, USA","institution_ids":["https://openalex.org/I78577930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043626288","display_name":"Sampada Sonalkar","orcid":null},"institutions":[{"id":"https://openalex.org/I78577930","display_name":"Columbia University","ror":"https://ror.org/00hj8s172","country_code":"US","type":"education","lineage":["https://openalex.org/I78577930"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sampada Sonalkar","raw_affiliation_strings":["Department of Computer Science, Columbia University, New York, NY, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Columbia University, New York, NY, USA","institution_ids":["https://openalex.org/I78577930"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5009992367","display_name":"Luca P. Carloni","orcid":"https://orcid.org/0000-0001-5600-8931"},"institutions":[{"id":"https://openalex.org/I78577930","display_name":"Columbia University","ror":"https://ror.org/00hj8s172","country_code":"US","type":"education","lineage":["https://openalex.org/I78577930"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Luca P Carloni","raw_affiliation_strings":["Department of Computer Science, Columbia University, New York, NY, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Columbia University, New York, NY, USA","institution_ids":["https://openalex.org/I78577930"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5003710372"],"corresponding_institution_ids":["https://openalex.org/I78577930"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.37197839,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"20","issue":null,"first_page":"1291","last_page":"1296"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.7619523406028748},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7520574331283569},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7486798763275146},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.6527936458587646},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.6232409477233887},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.5141668319702148},{"id":"https://openalex.org/keywords/cluster-analysis","display_name":"Cluster analysis","score":0.4664696156978607},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.45206934213638306},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4300328195095062},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4245932400226593},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.41829216480255127},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3745719790458679},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2569710910320282},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12147867679595947}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.7619523406028748},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7520574331283569},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7486798763275146},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.6527936458587646},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.6232409477233887},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.5141668319702148},{"id":"https://openalex.org/C73555534","wikidata":"https://www.wikidata.org/wiki/Q622825","display_name":"Cluster analysis","level":2,"score":0.4664696156978607},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.45206934213638306},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4300328195095062},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4245932400226593},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.41829216480255127},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3745719790458679},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2569710910320282},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12147867679595947},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/date.2010.5457005","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2010.5457005","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","raw_type":"proceedings-article"},{"id":"pmh:oai:academiccommons.columbia.edu:10.7916/D8B85G0K","is_oa":false,"landing_page_url":"https://doi.org/10.7916/D8B85G0K","pdf_url":null,"source":{"id":"https://openalex.org/S4306402601","display_name":"Columbia Academic Commons (Columbia University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I78577930","host_organization_name":"Columbia University","host_organization_lineage":["https://openalex.org/I78577930"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Reports"},{"id":"doi:10.7916/d8b85g0k","is_oa":true,"landing_page_url":"https://doi.org/10.7916/d8b85g0k","pdf_url":null,"source":{"id":"https://openalex.org/S4306402601","display_name":"Columbia Academic Commons (Columbia University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I78577930","host_organization_name":"Columbia University","host_organization_lineage":["https://openalex.org/I78577930"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"article-journal"}],"best_oa_location":{"id":"doi:10.7916/d8b85g0k","is_oa":true,"landing_page_url":"https://doi.org/10.7916/d8b85g0k","pdf_url":null,"source":{"id":"https://openalex.org/S4306402601","display_name":"Columbia Academic Commons (Columbia University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I78577930","host_organization_name":"Columbia University","host_organization_lineage":["https://openalex.org/I78577930"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"article-journal"},"sustainable_development_goals":[{"display_name":"Sustainable cities and communities","score":0.6600000262260437,"id":"https://metadata.un.org/sdg/11"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1999823427","https://openalex.org/W2022898841","https://openalex.org/W2076398447","https://openalex.org/W2097749327","https://openalex.org/W2099552965","https://openalex.org/W2102159907","https://openalex.org/W2104869032","https://openalex.org/W2108428835","https://openalex.org/W2114772983","https://openalex.org/W2132915653","https://openalex.org/W2133809797","https://openalex.org/W2136305336","https://openalex.org/W2147071478","https://openalex.org/W2150377841","https://openalex.org/W2151415616","https://openalex.org/W2155230244","https://openalex.org/W2160566592","https://openalex.org/W2160651385","https://openalex.org/W2163847543","https://openalex.org/W2171825402","https://openalex.org/W4230398107","https://openalex.org/W4233187670","https://openalex.org/W4246125513","https://openalex.org/W6676381999"],"related_works":["https://openalex.org/W2055008360","https://openalex.org/W1500063550","https://openalex.org/W2135118255","https://openalex.org/W215057456","https://openalex.org/W2106366463","https://openalex.org/W1535718467","https://openalex.org/W2165891825","https://openalex.org/W2942050196","https://openalex.org/W4251805775","https://openalex.org/W4239364405"],"abstract_inverted_index":{"We":[0],"present":[1],"a":[2,6,26,30,48,75,152,157,164],"throughput-driven":[3],"partitioning":[4,65],"and":[5,40,58,96,115,163],"throughput-preserving":[7],"merging":[8,126],"algorithm":[9,66,105,127],"for":[10,100],"the":[11,55,59,71,122,129,137,146],"high-level":[12],"physical":[13,33,60],"synthesis":[14,34,45],"of":[15,51,62,70,74,86,131],"latency-insensitive":[16],"(LI)":[17],"systems.":[18],"These":[19],"two":[20],"algorithms":[21],"are":[22],"integrated":[23],"along":[24],"with":[25],"published":[27],"floorplanner":[28],"in":[29,116,160,167],"new":[31],"iterative":[32],"flow":[35,46],"to":[36,53,79,94,106],"optimize":[37],"system":[38,56,147,161],"throughput":[39,119,162],"reduce":[41],"area":[42,139,168],"occupation.":[43,169],"The":[44,64,125],"iterates":[47],"floorplanning-partitioning-floorplanning-merging":[49],"sequence":[50],"operations":[52],"improve":[54],"topology":[57],"locations":[61],"cores.":[63],"performs":[67],"bottom-up":[68],"clustering":[69],"internal":[72],"logic":[73],"given":[76],"IP":[77],"core":[78],"divide":[80],"it":[81],"into":[82],"smaller":[83],"ones,":[84],"each":[85],"which":[87],"has":[88],"no":[89],"combinational":[90],"path":[91],"from":[92],"input":[93],"output":[95],"thus":[97],"is":[98],"legal":[99],"LI-interface":[101],"encapsulation.":[102],"Applying":[103],"this":[104],"cores":[107,132],"on":[108,133,151],"critical":[109],"feedback":[110],"loops":[111],"optimizes":[112],"their":[113],"length":[114],"turn":[117],"enables":[118],"optimization":[120],"via":[121],"subsequent":[123],"floorplanning.":[124],"reduces":[128],"number":[130],"non-critical":[134],"loops,":[135],"lowering":[136],"overall":[138],"taken":[140],"by":[141],"LI":[142],"interfaces":[143],"without":[144],"hurting":[145],"throughput.":[148],"Experimental":[149],"results":[150],"large":[153],"system-on-chip":[154],"design":[155],"show":[156],"16.7%":[158],"speedup":[159],"2.1%":[165],"reduction":[166]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-02-09T09:26:11.010843","created_date":"2025-10-10T00:00:00"}