{"id":"https://openalex.org/W4234147560","doi":"https://doi.org/10.1109/date.2004.1269008","title":"Memmap: technology mapping algorithm for area reduction in FPGAs with embedded memory arrays using reconvergence analysis","display_name":"Memmap: technology mapping algorithm for area reduction in FPGAs with embedded memory arrays using reconvergence analysis","publication_year":2004,"publication_date":"2004-07-20","ids":{"openalex":"https://openalex.org/W4234147560","doi":"https://doi.org/10.1109/date.2004.1269008"},"language":"en","primary_location":{"id":"doi:10.1109/date.2004.1269008","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1269008","pdf_url":null,"source":{"id":"https://openalex.org/S4363608792","display_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090926092","display_name":"A. Manoj Kumar","orcid":null},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"facility","lineage":["https://openalex.org/I24676775"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"A. Manoj Kumar","raw_affiliation_strings":["Indian Institute of Technology Madras"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Madras","institution_ids":["https://openalex.org/I24676775"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089900935","display_name":"J. Bobba","orcid":null},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"facility","lineage":["https://openalex.org/I24676775"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"J. Bobba","raw_affiliation_strings":["Indian Institute of Technology Madras, India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Madras, India","institution_ids":["https://openalex.org/I24676775"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5046715331","display_name":"V. Kamakoti","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"V. Kamakoti","raw_affiliation_strings":[],"affiliations":[]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5090926092"],"corresponding_institution_ids":["https://openalex.org/I24676775"],"apc_list":null,"apc_paid":null,"fwci":0.5091,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.57870895,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"19","issue":null,"first_page":"922","last_page":"927"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.986299991607666,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.986299991607666,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9857000112533569,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10624","display_name":"Silicon and Solar Cell Technologies","score":0.9476000070571899,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8397538661956787},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.774136483669281},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.7554032206535339},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.7383856773376465},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.722971498966217},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4728693664073944},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4519276022911072},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4488181173801422},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4148472249507904},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.37680408358573914},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.36974257230758667},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.36448395252227783},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11701208353042603},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08757206797599792},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.06212857365608215}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8397538661956787},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.774136483669281},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.7554032206535339},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.7383856773376465},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.722971498966217},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4728693664073944},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4519276022911072},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4488181173801422},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4148472249507904},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.37680408358573914},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.36974257230758667},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.36448395252227783},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11701208353042603},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08757206797599792},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.06212857365608215},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2004.1269008","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1269008","pdf_url":null,"source":{"id":"https://openalex.org/S4363608792","display_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1969802502","https://openalex.org/W1978998136","https://openalex.org/W1985856707","https://openalex.org/W2105355057","https://openalex.org/W2105715355","https://openalex.org/W2108539060","https://openalex.org/W2124456496","https://openalex.org/W2144736151","https://openalex.org/W2161582063","https://openalex.org/W2167328871","https://openalex.org/W4252590738"],"related_works":["https://openalex.org/W2024574431","https://openalex.org/W2117300767","https://openalex.org/W2374017528","https://openalex.org/W4285503609","https://openalex.org/W2126248441","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2160474882","https://openalex.org/W2125609625"],"abstract_inverted_index":{"Modern":[0],"day":[1],"field":[2],"programmable":[3],"gate":[4],"arrays":[5],"(FPGA)":[6],"include":[7],"in":[8,88,95,125,134],"addition":[9],"to":[10,20,22,36,52,61,75,91,121],"look-up":[11,59,80],"tables,":[12],"reasonably":[13],"big":[14],"configurable":[15],"embedded":[16],"memory":[17,25],"blocks":[18],"(EMB)":[19],"cater":[21],"the":[23,41,67,85,96,99,135],"on-chip":[24],"requirements":[26],"of":[27,40,66,78,98],"systems/applications":[28],"mapped":[29,73],"on":[30,35,74,84,115],"them.":[31],"While":[32],"mapping":[33,103],"applications":[34],"such":[37,54],"FPGAs,":[38],"some":[39],"EMBs":[42,56],"may":[43],"be":[44,72],"left":[45],"unused.":[46],"This":[47,87],"paper":[48],"presents":[49],"a":[50,76,92],"methodology":[51],"utilize":[53],"unused":[55],"as":[57],"large":[58],"tables":[60,81],"map":[62],"multi-output":[63],"combinational":[64],"sub-circuits":[65],"application,":[68],"which,":[69],"otherwise":[70],"would":[71],"number":[77],"small":[79],"(LUT)":[82],"available":[83],"FPGA.":[86],"turn":[89],"leads":[90],"huge":[93],"reduction":[94,124],"area":[97,126],"FPGA,":[100],"utilized":[101,127],"for":[102],"an":[104],"application.":[105],"Experimental":[106],"results":[107],"show":[108],"that":[109],"our":[110],"proposed":[111],"methodology,":[112],"when":[113,128],"employed":[114],"popular":[116],"benchmark":[117],"circuits,":[118],"can":[119],"lead":[120],"additional":[122],"50%":[123],"compared":[129],"with":[130],"other":[131],"methodologies":[132],"reported":[133],"literature.":[136]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
