{"id":"https://openalex.org/W4235685344","doi":"https://doi.org/10.1109/date.2002.998443","title":"Concurrent and selective logic extraction with timing consideration","display_name":"Concurrent and selective logic extraction with timing consideration","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W4235685344","doi":"https://doi.org/10.1109/date.2002.998443"},"language":"en","primary_location":{"id":"doi:10.1109/date.2002.998443","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2002.998443","pdf_url":null,"source":{"id":"https://openalex.org/S4363608838","display_name":"Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5073367744","display_name":"P. Rezvani","orcid":null},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"P. Rezvani","raw_affiliation_strings":["University of Southern California, Los Angeles, CA, USA"],"affiliations":[{"raw_affiliation_string":"University of Southern California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I1174212"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007613289","display_name":"M. Pedram","orcid":null},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Pedram","raw_affiliation_strings":["University of Southern California, Los Angeles, CA, USA"],"affiliations":[{"raw_affiliation_string":"University of Southern California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I1174212"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5073367744"],"corresponding_institution_ids":["https://openalex.org/I1174212"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.36603774,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1086","last_page":"1086"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9936000108718872,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11567","display_name":"semigroups and automata theory","score":0.9908000230789185,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/heuristics","display_name":"Heuristics","score":0.7625049352645874},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6886250972747803},{"id":"https://openalex.org/keywords/literal","display_name":"Literal (mathematical logic)","score":0.5935388803482056},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.4984312057495117},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4737994074821472},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.46675539016723633},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.44189855456352234},{"id":"https://openalex.org/keywords/boolean-circuit","display_name":"Boolean circuit","score":0.4343523383140564},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.43153274059295654},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.3847529888153076},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.34591034054756165},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.11001041531562805}],"concepts":[{"id":"https://openalex.org/C127705205","wikidata":"https://www.wikidata.org/wiki/Q5748245","display_name":"Heuristics","level":2,"score":0.7625049352645874},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6886250972747803},{"id":"https://openalex.org/C2780882242","wikidata":"https://www.wikidata.org/wiki/Q14235582","display_name":"Literal (mathematical logic)","level":2,"score":0.5935388803482056},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.4984312057495117},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4737994074821472},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.46675539016723633},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.44189855456352234},{"id":"https://openalex.org/C141796577","wikidata":"https://www.wikidata.org/wiki/Q837479","display_name":"Boolean circuit","level":3,"score":0.4343523383140564},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.43153274059295654},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3847529888153076},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.34591034054756165},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.11001041531562805},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2002.998443","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2002.998443","pdf_url":null,"source":{"id":"https://openalex.org/S4363608838","display_name":"Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W2152173554"],"related_works":["https://openalex.org/W1966764473","https://openalex.org/W2098419840","https://openalex.org/W2614722573","https://openalex.org/W2121963733","https://openalex.org/W2798487558","https://openalex.org/W2789349722","https://openalex.org/W1977171228","https://openalex.org/W2102927888","https://openalex.org/W4249951793","https://openalex.org/W2170504327"],"abstract_inverted_index":{"We":[0,14,40],"study":[1],"the":[2,17,47,72,84],"problem":[3,18,36],"of":[4,71],"concurrent":[5],"and":[6,27,62],"selective":[7],"logic":[8,51],"extraction":[9,52,73],"in":[10,37],"a":[11,32,38,67,80],"Boolean":[12],"circuit.":[13],"first":[15],"model":[16],"using":[19],"graph":[20],"theory,":[21],"prove":[22],"it":[23,30],"to":[24,57,66],"be":[25],"NP-hard,":[26],"subsequently":[28],"formulate":[29],"as":[31],"Maximum-Weight":[33],"Independent":[34],"Set":[35],"graph.":[39],"then":[41],"use":[42],"efficient":[43],"heuristics":[44],"for":[45,82],"solving":[46],"MWIS":[48],"problem.":[49],"Concurrent":[50],"not":[53],"only":[54],"allows":[55],"us":[56,78],"achieve":[58],"larger":[59],"literal":[60],"saving":[61],"smaller":[63],"area":[64],"due":[65],"more":[68],"global":[69],"view":[70],"space,":[74],"but":[75],"also":[76],"provides":[77],"with":[79],"framework":[81],"reducing":[83],"circuit":[85],"delay.":[86]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}