{"id":"https://openalex.org/W4241251637","doi":"https://doi.org/10.1109/date.1999.761175","title":"Integrating symbolic techniques in ATPG-based sequential logic optimization","display_name":"Integrating symbolic techniques in ATPG-based sequential logic optimization","publication_year":2003,"publication_date":"2003-01-20","ids":{"openalex":"https://openalex.org/W4241251637","doi":"https://doi.org/10.1109/date.1999.761175"},"language":"en","primary_location":{"id":"doi:10.1109/date.1999.761175","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.1999.761175","pdf_url":null,"source":{"id":"https://openalex.org/S4363608933","display_name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"E. San Millan","orcid":null},"institutions":[{"id":"https://openalex.org/I50357001","display_name":"Universidad Carlos III de Madrid","ror":"https://ror.org/03ths8210","country_code":"ES","type":"education","lineage":["https://openalex.org/I50357001"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"E. San Millan","raw_affiliation_strings":["Dpto. de Ingener\u00eda El\u00e9ctrica, Electr\u00f3nica y Autom\u00e1tica, Universidad Carlos III de Madrid, Spain"],"affiliations":[{"raw_affiliation_string":"Dpto. de Ingener\u00eda El\u00e9ctrica, Electr\u00f3nica y Autom\u00e1tica, Universidad Carlos III de Madrid, Spain","institution_ids":["https://openalex.org/I50357001"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022411878","display_name":"Luis Entrena","orcid":"https://orcid.org/0000-0001-6021-165X"},"institutions":[{"id":"https://openalex.org/I50357001","display_name":"Universidad Carlos III de Madrid","ror":"https://ror.org/03ths8210","country_code":"ES","type":"education","lineage":["https://openalex.org/I50357001"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"L. Entrena","raw_affiliation_strings":["Dpto. de Ingener\u00eda El\u00e9ctrica, Electr\u00f3nica y Autom\u00e1tica, Universidad Carlos III de Madrid, Spain"],"affiliations":[{"raw_affiliation_string":"Dpto. de Ingener\u00eda El\u00e9ctrica, Electr\u00f3nica y Autom\u00e1tica, Universidad Carlos III de Madrid, Spain","institution_ids":["https://openalex.org/I50357001"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021597287","display_name":"J.A. Espejo","orcid":null},"institutions":[{"id":"https://openalex.org/I50357001","display_name":"Universidad Carlos III de Madrid","ror":"https://ror.org/03ths8210","country_code":"ES","type":"education","lineage":["https://openalex.org/I50357001"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"J.A. Espejo","raw_affiliation_strings":["Dpto. de Ingener\u00eda El\u00e9ctrica, Electr\u00f3nica y Autom\u00e1tica, Universidad Carlos III de Madrid, Spain"],"affiliations":[{"raw_affiliation_string":"Dpto. de Ingener\u00eda El\u00e9ctrica, Electr\u00f3nica y Autom\u00e1tica, Universidad Carlos III de Madrid, Spain","institution_ids":["https://openalex.org/I50357001"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091589252","display_name":"Silvia Chiusano","orcid":"https://orcid.org/0000-0002-5740-5004"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"S. Chiusano","raw_affiliation_strings":["Dipartimento di Automatica e Informatica, Politecnico di Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5060510787","display_name":"Fulvio Corno","orcid":"https://orcid.org/0000-0002-9818-0999"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"F. Corno","raw_affiliation_strings":["Dipartimento di Automatica e Informatica, Politecnico di Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I50357001"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.30788804,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"516","last_page":"520"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.9003649950027466},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6680525541305542},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.5939736366271973},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5523029565811157},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.5264649987220764},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5117599964141846},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4492199122905731},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4441802501678467},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3276674747467041},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11690139770507812}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.9003649950027466},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6680525541305542},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.5939736366271973},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5523029565811157},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.5264649987220764},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5117599964141846},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4492199122905731},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4441802501678467},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3276674747467041},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11690139770507812},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.1999.761175","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.1999.761175","pdf_url":null,"source":{"id":"https://openalex.org/S4363608933","display_name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W142838967","https://openalex.org/W1754966200","https://openalex.org/W2000670199","https://openalex.org/W2030224590","https://openalex.org/W2061438988","https://openalex.org/W2096554094","https://openalex.org/W2115571162","https://openalex.org/W2119627643","https://openalex.org/W2125651818","https://openalex.org/W2137492815","https://openalex.org/W2170227286","https://openalex.org/W4231903556","https://openalex.org/W4247308647","https://openalex.org/W4252494805","https://openalex.org/W6665773200"],"related_works":["https://openalex.org/W2386022279","https://openalex.org/W2113700423","https://openalex.org/W3129977055","https://openalex.org/W2108229542","https://openalex.org/W3148292035","https://openalex.org/W2370649629","https://openalex.org/W1966764473","https://openalex.org/W2362510906","https://openalex.org/W1984491986","https://openalex.org/W1488117239"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3],"new":[4],"integrated":[5,47],"approach":[6,14,48,91],"to":[7,56,76,92],"logic":[8,78],"optimization":[9,79,96],"for":[10],"sequential":[11,64],"circuits.":[12],"The":[13,43],"is":[15,25,73],"based":[16,26,40],"on":[17,27,41],"the":[18,46,51,63,67,70,77,87,90,93],"redundancy":[19],"addition":[20],"and":[21,34,59],"removal":[22],"algorithm,":[23],"which":[24],"automatic":[28],"test":[29],"pattern":[30],"generation":[31],"(ATPG)":[32],"techniques,":[33],"improves":[35],"it":[36],"using":[37],"symbolic":[38],"techniques":[39],"BDDs.":[42],"advantage":[44],"of":[45,53,66,69,74,89],"lies":[49],"in":[50],"ability":[52],"Symbolic":[54],"Techniques":[55],"provide":[57],"exact":[58],"extensive":[60],"information":[61],"about":[62],"behavior":[65],"portion":[68],"circuit":[71],"that":[72,85],"interest":[75],"algorithm.":[80],"Experimental":[81],"results":[82],"are":[83],"provided":[84],"show":[86],"superiority":[88],"original":[94],"ATPG-based":[95],"approach.":[97]},"counts_by_year":[],"updated_date":"2026-04-16T08:26:57.006410","created_date":"2025-10-10T00:00:00"}