{"id":"https://openalex.org/W1601026578","doi":"https://doi.org/10.1109/dasip.2014.7115604","title":"Hardware realization of an FPGA processor — Operating system call offload and experiences","display_name":"Hardware realization of an FPGA processor — Operating system call offload and experiences","publication_year":2014,"publication_date":"2014-10-01","ids":{"openalex":"https://openalex.org/W1601026578","doi":"https://doi.org/10.1109/dasip.2014.7115604","mag":"1601026578"},"language":"en","primary_location":{"id":"doi:10.1109/dasip.2014.7115604","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dasip.2014.7115604","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5004076027","display_name":"Andreas Erik Hindborg","orcid":null},"institutions":[{"id":"https://openalex.org/I96673099","display_name":"Technical University of Denmark","ror":"https://ror.org/04qtj9h94","country_code":"DK","type":"education","lineage":["https://openalex.org/I96673099"]}],"countries":["DK"],"is_corresponding":true,"raw_author_name":"Andreas Erik Hindborg","raw_affiliation_strings":["DTU Compute \u2013 Technical University of Denmark","DTU Compute Technical University of Denmark"],"affiliations":[{"raw_affiliation_string":"DTU Compute \u2013 Technical University of Denmark","institution_ids":["https://openalex.org/I96673099"]},{"raw_affiliation_string":"DTU Compute Technical University of Denmark","institution_ids":["https://openalex.org/I96673099"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025031001","display_name":"Pascal Schleuniger","orcid":null},"institutions":[{"id":"https://openalex.org/I96673099","display_name":"Technical University of Denmark","ror":"https://ror.org/04qtj9h94","country_code":"DK","type":"education","lineage":["https://openalex.org/I96673099"]}],"countries":["DK"],"is_corresponding":false,"raw_author_name":"Pascal Schleuniger","raw_affiliation_strings":["DTU Compute \u2013 Technical University of Denmark","DTU Compute Technical University of Denmark"],"affiliations":[{"raw_affiliation_string":"DTU Compute \u2013 Technical University of Denmark","institution_ids":["https://openalex.org/I96673099"]},{"raw_affiliation_string":"DTU Compute Technical University of Denmark","institution_ids":["https://openalex.org/I96673099"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085572561","display_name":"Nicklas Bo Jensen","orcid":"https://orcid.org/0000-0003-1528-7748"},"institutions":[{"id":"https://openalex.org/I96673099","display_name":"Technical University of Denmark","ror":"https://ror.org/04qtj9h94","country_code":"DK","type":"education","lineage":["https://openalex.org/I96673099"]}],"countries":["DK"],"is_corresponding":false,"raw_author_name":"Nicklas Bo Jensen","raw_affiliation_strings":["DTU Compute \u2013 Technical University of Denmark","DTU Compute Technical University of Denmark"],"affiliations":[{"raw_affiliation_string":"DTU Compute \u2013 Technical University of Denmark","institution_ids":["https://openalex.org/I96673099"]},{"raw_affiliation_string":"DTU Compute Technical University of Denmark","institution_ids":["https://openalex.org/I96673099"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5048021485","display_name":"Sven Karlsson","orcid":"https://orcid.org/0000-0003-0737-9992"},"institutions":[{"id":"https://openalex.org/I96673099","display_name":"Technical University of Denmark","ror":"https://ror.org/04qtj9h94","country_code":"DK","type":"education","lineage":["https://openalex.org/I96673099"]}],"countries":["DK"],"is_corresponding":false,"raw_author_name":"Sven Karlsson","raw_affiliation_strings":["DTU Compute \u2013 Technical University of Denmark","DTU Compute Technical University of Denmark"],"affiliations":[{"raw_affiliation_string":"DTU Compute \u2013 Technical University of Denmark","institution_ids":["https://openalex.org/I96673099"]},{"raw_affiliation_string":"DTU Compute Technical University of Denmark","institution_ids":["https://openalex.org/I96673099"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5004076027"],"corresponding_institution_ids":["https://openalex.org/I96673099"],"apc_list":null,"apc_paid":null,"fwci":0.9194,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.73186092,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"7179","issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/microblaze","display_name":"MicroBlaze","score":0.8828140497207642},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8105329275131226},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7974459528923035},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.5987091064453125},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5934047102928162},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5349339842796326},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.47277191281318665},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.4370940923690796},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3409695625305176},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.2843455970287323}],"concepts":[{"id":"https://openalex.org/C2777575374","wikidata":"https://www.wikidata.org/wiki/Q1644704","display_name":"MicroBlaze","level":3,"score":0.8828140497207642},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8105329275131226},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7974459528923035},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.5987091064453125},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5934047102928162},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5349339842796326},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.47277191281318665},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.4370940923690796},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3409695625305176},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2843455970287323}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dasip.2014.7115604","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dasip.2014.7115604","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.47999998927116394}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W12207660","https://openalex.org/W39695077","https://openalex.org/W122440332","https://openalex.org/W136905915","https://openalex.org/W184921283","https://openalex.org/W1479772908","https://openalex.org/W1567646530","https://openalex.org/W1990079240","https://openalex.org/W2036853599","https://openalex.org/W2108157916","https://openalex.org/W2116299797","https://openalex.org/W2125744812","https://openalex.org/W2140311411","https://openalex.org/W2145021036","https://openalex.org/W2533368764","https://openalex.org/W4238549726","https://openalex.org/W6605013814","https://openalex.org/W6628758338"],"related_works":["https://openalex.org/W2371772824","https://openalex.org/W2350519679","https://openalex.org/W2058965144","https://openalex.org/W2164382479","https://openalex.org/W2169881414","https://openalex.org/W2376312311","https://openalex.org/W2354823813","https://openalex.org/W3012895752","https://openalex.org/W1970479385","https://openalex.org/W2143461502"],"abstract_inverted_index":{"Field-programmable":[0],"gate":[1],"arrays,":[2],"FPGAs,":[3],"are":[4],"attractive":[5],"implementation":[6,23,129],"platforms":[7,91],"for":[8,20,43],"low-volume":[9],"signal":[10,87],"and":[11,55,88,112],"image":[12],"processing":[13,90],"applications.":[14],"The":[15],"structure":[16],"of":[17,24,63,74,110,120],"FPGAs":[18],"allows":[19],"an":[21,64],"efficient":[22],"parallel":[25,61],"algorithms.":[26],"Sequential":[27],"algorithms,":[28],"on":[29,36,92],"the":[30,71,100],"other":[31],"hand,":[32],"often":[33],"perform":[34],"better":[35],"a":[37,48,76,108,118,125],"microprocessor.":[38],"It":[39],"is":[40],"therefore":[41],"convenient":[42],"many":[44,86],"applications":[45],"to":[46,51,59,102,122,133],"employ":[47],"synthesizable":[49,78],"microprocessor":[50],"execute":[52],"sequential":[53],"tasks":[54],"custom":[56],"hardware":[57,72,136],"structures":[58],"accelerate":[60],"sections":[62],"algorithm.":[65],"In":[66],"this":[67],"paper,":[68],"we":[69,98,116],"discuss":[70],"realization":[73],"Tinuso-I,":[75],"small":[77],"processor":[79,101],"core":[80],"that":[81],"can":[82],"be":[83],"integrated":[84],"in":[85],"data":[89],"FPGAs.":[93],"We":[94],"also":[95],"show":[96,117],"how":[97],"allow":[99],"use":[103],"operating":[104],"system":[105],"services.":[106],"For":[107],"set":[109],"SPLASH-2":[111],"SPEC":[113],"CPU2006":[114],"benchmarks":[115],"speedup":[119],"up":[121],"64%":[123],"over":[124],"similar":[126],"Xilinx":[127],"MicroBlaze":[128],"while":[130],"using":[131],"27%":[132],"35%":[134],"fewer":[135],"resources.":[137]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}