{"id":"https://openalex.org/W2084238511","doi":"https://doi.org/10.1109/dasc.2013.75","title":"A New System Interconnection Architecture Based on RapidIO Using Partial Reconfiguration","display_name":"A New System Interconnection Architecture Based on RapidIO Using Partial Reconfiguration","publication_year":2013,"publication_date":"2013-12-01","ids":{"openalex":"https://openalex.org/W2084238511","doi":"https://doi.org/10.1109/dasc.2013.75","mag":"2084238511"},"language":"en","primary_location":{"id":"doi:10.1109/dasc.2013.75","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dasc.2013.75","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 11th International Conference on Dependable, Autonomic and Secure Computing","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050256911","display_name":"Zhan Xu","orcid":"https://orcid.org/0000-0001-5301-9600"},"institutions":[{"id":"https://openalex.org/I17145004","display_name":"Northwestern Polytechnical University","ror":"https://ror.org/01y0j0j86","country_code":"CN","type":"education","lineage":["https://openalex.org/I17145004"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhan Xu","raw_affiliation_strings":["School of Computer Science and Engineering, NorthWestern Polytechnical University, Xi'an, China","Sch. of Comput. Sci. & Eng., NorthWestern Polytech. Univ., Xi'an, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer Science and Engineering, NorthWestern Polytechnical University, Xi'an, China","institution_ids":["https://openalex.org/I17145004"]},{"raw_affiliation_string":"Sch. of Comput. Sci. & Eng., NorthWestern Polytech. Univ., Xi'an, China","institution_ids":["https://openalex.org/I17145004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072397998","display_name":"Xiao Wu","orcid":"https://orcid.org/0000-0002-4884-657X"},"institutions":[{"id":"https://openalex.org/I17145004","display_name":"Northwestern Polytechnical University","ror":"https://ror.org/01y0j0j86","country_code":"CN","type":"education","lineage":["https://openalex.org/I17145004"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiao Wu","raw_affiliation_strings":["School of Computer Science and Engineering, NorthWestern Polytechnical University, Xi'an, China","Sch. of Comput. Sci. & Eng., NorthWestern Polytech. Univ., Xi'an, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer Science and Engineering, NorthWestern Polytechnical University, Xi'an, China","institution_ids":["https://openalex.org/I17145004"]},{"raw_affiliation_string":"Sch. of Comput. Sci. & Eng., NorthWestern Polytech. Univ., Xi'an, China","institution_ids":["https://openalex.org/I17145004"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030352944","display_name":"Yi Wu","orcid":"https://orcid.org/0000-0002-4761-7791"},"institutions":[{"id":"https://openalex.org/I17145004","display_name":"Northwestern Polytechnical University","ror":"https://ror.org/01y0j0j86","country_code":"CN","type":"education","lineage":["https://openalex.org/I17145004"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yi Wu","raw_affiliation_strings":["School of Computer Science and Engineering, NorthWestern Polytechnical University, Xi'an, China","Sch. of Comput. Sci. & Eng., NorthWestern Polytech. Univ., Xi'an, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer Science and Engineering, NorthWestern Polytechnical University, Xi'an, China","institution_ids":["https://openalex.org/I17145004"]},{"raw_affiliation_string":"Sch. of Comput. Sci. & Eng., NorthWestern Polytech. Univ., Xi'an, China","institution_ids":["https://openalex.org/I17145004"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I17145004"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.16016881,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"51","issue":null,"first_page":"275","last_page":"279"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9947999715805054,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8496983051300049},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.8020159602165222},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7731854319572449},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.6957546472549438},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6872301697731018},{"id":"https://openalex.org/keywords/partition","display_name":"Partition (number theory)","score":0.5765804052352905},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5311029553413391},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.4785500168800354},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.47686466574668884},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.205558180809021},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1283189058303833}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8496983051300049},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.8020159602165222},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7731854319572449},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.6957546472549438},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6872301697731018},{"id":"https://openalex.org/C42812","wikidata":"https://www.wikidata.org/wiki/Q1082910","display_name":"Partition (number theory)","level":2,"score":0.5765804052352905},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5311029553413391},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.4785500168800354},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.47686466574668884},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.205558180809021},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1283189058303833},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dasc.2013.75","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dasc.2013.75","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 11th International Conference on Dependable, Autonomic and Secure Computing","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5799999833106995,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W2005971517","https://openalex.org/W2035695620","https://openalex.org/W2348200245","https://openalex.org/W2494353872"],"related_works":["https://openalex.org/W2808484818","https://openalex.org/W2810427553","https://openalex.org/W2135053878","https://openalex.org/W2941434274","https://openalex.org/W2340647897","https://openalex.org/W4249632163","https://openalex.org/W1760305469","https://openalex.org/W2797161794","https://openalex.org/W2073075351","https://openalex.org/W2096938998"],"abstract_inverted_index":{"Now":[0],"in":[1,28,55],"the":[2,23,29,48,52,65,70,97],"field":[3],"of":[4,21],"embedded":[5],"system,":[6],"high-speed":[7],"interconnection":[8,35,90],"based":[9,92],"on":[10,93],"parallel":[11],"or":[12],"serial":[13],"LVDS":[14],"technology":[15],"is":[16,78],"becoming":[17],"increasingly":[18],"important.":[19],"Because":[20],"this":[22],"first":[24],"RapidIO":[25,34,67,94],"offerings":[26],"available":[27],"market":[30],"were":[31],"FPGA":[32,98],"based,":[33],"had":[36],"been":[37],"identified":[38],"as":[39,51],"significant":[40],"emerging":[41],"technologies":[42],"for":[43],"FPGAs":[44,53],"to":[45,62,80,95],"support.":[46],"At":[47],"same":[49],"time,":[50],"increase":[54],"size,":[56],"they":[57],"are":[58],"being":[59],"large":[60],"enough":[61],"accommodate":[63],"both":[64],"static":[66],"interface":[68,77],"and":[69],"reconfigurable":[71],"logic.":[72],"So,":[73],"a":[74,87],"consistent":[75],"I/O":[76],"provided":[79],"support":[81],"Reconfigurable":[82,100],"Partition.":[83,101],"This":[84],"paper":[85],"presents":[86],"new":[88],"system":[89],"architecture":[91],"achieve":[96],"run-time":[99]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}