{"id":"https://openalex.org/W4414199206","doi":"https://doi.org/10.1109/dac63849.2025.11132799","title":"SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits","display_name":"SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits","publication_year":2025,"publication_date":"2025-06-22","ids":{"openalex":"https://openalex.org/W4414199206","doi":"https://doi.org/10.1109/dac63849.2025.11132799"},"language":"en","primary_location":{"id":"doi:10.1109/dac63849.2025.11132799","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dac63849.2025.11132799","pdf_url":null,"source":null,"license":"public-domain","license_id":"https://openalex.org/licenses/public-domain","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 62nd ACM/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101520717","display_name":"Shang Liu","orcid":"https://orcid.org/0009-0000-0057-7844"},"institutions":[{"id":"https://openalex.org/I200769079","display_name":"Hong Kong University of Science and Technology","ror":"https://ror.org/00q4vv597","country_code":"HK","type":"education","lineage":["https://openalex.org/I200769079"]}],"countries":["HK"],"is_corresponding":true,"raw_author_name":"Shang Liu","raw_affiliation_strings":["Hong Kong University of Science and Technology"],"affiliations":[{"raw_affiliation_string":"Hong Kong University of Science and Technology","institution_ids":["https://openalex.org/I200769079"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100378565","display_name":"Jing Wang","orcid":"https://orcid.org/0000-0002-6880-4481"},"institutions":[{"id":"https://openalex.org/I200769079","display_name":"Hong Kong University of Science and Technology","ror":"https://ror.org/00q4vv597","country_code":"HK","type":"education","lineage":["https://openalex.org/I200769079"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Jing Wang","raw_affiliation_strings":["Hong Kong University of Science and Technology"],"affiliations":[{"raw_affiliation_string":"Hong Kong University of Science and Technology","institution_ids":["https://openalex.org/I200769079"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102873255","display_name":"Wenji Fang","orcid":"https://orcid.org/0000-0002-8380-9395"},"institutions":[{"id":"https://openalex.org/I200769079","display_name":"Hong Kong University of Science and Technology","ror":"https://ror.org/00q4vv597","country_code":"HK","type":"education","lineage":["https://openalex.org/I200769079"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Wenji Fang","raw_affiliation_strings":["Hong Kong University of Science and Technology"],"affiliations":[{"raw_affiliation_string":"Hong Kong University of Science and Technology","institution_ids":["https://openalex.org/I200769079"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101509934","display_name":"Zhiyao Xie","orcid":"https://orcid.org/0009-0005-4608-6895"},"institutions":[{"id":"https://openalex.org/I200769079","display_name":"Hong Kong University of Science and Technology","ror":"https://ror.org/00q4vv597","country_code":"HK","type":"education","lineage":["https://openalex.org/I200769079"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Zhiyao Xie","raw_affiliation_strings":["Hong Kong University of Science and Technology"],"affiliations":[{"raw_affiliation_string":"Hong Kong University of Science and Technology","institution_ids":["https://openalex.org/I200769079"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5101520717"],"corresponding_institution_ids":["https://openalex.org/I200769079"],"apc_list":null,"apc_paid":null,"fwci":0.6973,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.75661926,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9496999979019165,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9496999979019165,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.946399986743927,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9190000295639038,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.49709999561309814},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.46639999747276306},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.4625999927520752},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4618000090122223},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.43779999017715454},{"id":"https://openalex.org/keywords/synthetic-data","display_name":"Synthetic data","score":0.4296000003814697},{"id":"https://openalex.org/keywords/big-data","display_name":"Big data","score":0.41609999537467957},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.41519999504089355},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4000000059604645},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.38420000672340393}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7871999740600586},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.49709999561309814},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.46639999747276306},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.4625999927520752},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4618000090122223},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.43779999017715454},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4357999861240387},{"id":"https://openalex.org/C160920958","wikidata":"https://www.wikidata.org/wiki/Q7662746","display_name":"Synthetic data","level":2,"score":0.4296000003814697},{"id":"https://openalex.org/C75684735","wikidata":"https://www.wikidata.org/wiki/Q858810","display_name":"Big data","level":2,"score":0.41609999537467957},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.41519999504089355},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4000000059604645},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.38420000672340393},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.38280001282691956},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.35109999775886536},{"id":"https://openalex.org/C88468194","wikidata":"https://www.wikidata.org/wiki/Q1172416","display_name":"Data-flow analysis","level":3,"score":0.33340001106262207},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.33320000767707825},{"id":"https://openalex.org/C167966045","wikidata":"https://www.wikidata.org/wiki/Q5532625","display_name":"Generative model","level":3,"score":0.3253999948501587},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.3197999894618988},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.30630001425743103},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.3025999963283539},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.29510000348091125},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.2930999994277954},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.2912999987602234},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.28060001134872437},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.2766999900341034},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.27230000495910645},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.27140000462532043},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.26739999651908875},{"id":"https://openalex.org/C141796577","wikidata":"https://www.wikidata.org/wiki/Q837479","display_name":"Boolean circuit","level":3,"score":0.265500009059906},{"id":"https://openalex.org/C67186912","wikidata":"https://www.wikidata.org/wiki/Q367664","display_name":"Data modeling","level":2,"score":0.260699987411499},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.26019999384880066},{"id":"https://openalex.org/C179145894","wikidata":"https://www.wikidata.org/wiki/Q5264353","display_name":"Design layout record","level":5,"score":0.2596000134944916},{"id":"https://openalex.org/C46205389","wikidata":"https://www.wikidata.org/wiki/Q1270401","display_name":"Electronic circuit simulation","level":3,"score":0.2533000111579895},{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.2515000104904175}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/dac63849.2025.11132799","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dac63849.2025.11132799","pdf_url":null,"source":null,"license":"public-domain","license_id":"https://openalex.org/licenses/public-domain","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 62nd ACM/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"},{"id":"pmh:oai:repository.hkust.edu.hk:1783.1-151979","is_oa":false,"landing_page_url":"http://repository.hkust.edu.hk/ir/Record/1783.1-151979","pdf_url":null,"source":{"id":"https://openalex.org/S4306401796","display_name":"Rare & Special e-Zone (The Hong Kong University of Science and Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I200769079","host_organization_name":"Hong Kong University of Science and Technology","host_organization_lineage":["https://openalex.org/I200769079"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference paper"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W2124618076","https://openalex.org/W2126316555","https://openalex.org/W2150649057","https://openalex.org/W2984343629","https://openalex.org/W3027968530","https://openalex.org/W4281621614","https://openalex.org/W4289436753","https://openalex.org/W4381415966","https://openalex.org/W4389166667","https://openalex.org/W4403023622","https://openalex.org/W4404101791","https://openalex.org/W4404133510"],"related_works":[],"abstract_inverted_index":{"In":[0,42],"recent":[1],"years,":[2],"AI-assisted":[3,38],"IC":[4,39],"design":[5,16,40,158],"methods":[6],"have":[7],"demonstrated":[8],"great":[9],"potential,":[10],"but":[11],"the":[12,23,33,47,60,84,98,110,115,130,134],"availability":[13],"of":[14,28],"circuit":[15,29,105,111,157],"data":[17,30,66],"is":[18,106],"extremely":[19],"limited,":[20],"especially":[21],"in":[22,36,59,97,133,155],"public":[24],"domain.":[25],"The":[26,121],"lack":[27],"has":[31,92],"become":[32],"primary":[34],"bottleneck":[35],"developing":[37],"methods.":[41],"this":[43],"work,":[44],"we":[45,108],"make":[46],"first":[48],"attempt,":[49],"SynCircuit,":[50],"to":[51,82],"generate":[52,145],"new":[53],"synthetic":[54,65,148],"circuits":[55,149],"with":[56,70],"valid":[57],"functionalities":[58],"HDL":[61],"format.SynCircuit":[62],"automatically":[63],"generates":[64],"using":[67],"a":[68,77],"framework":[69],"three":[71],"innovative":[72],"steps:":[73],"1)":[74],"We":[75],"propose":[76],"customized":[78],"diffusion-based":[79],"generative":[80],"model":[81,153],"resolve":[83],"Directed":[85],"Cyclic":[86],"Graph":[87],"(DCG)":[88],"generation":[89,118],"task,":[90],"which":[91],"not":[93],"been":[94],"well":[95],"explored":[96],"AI":[99],"community.":[100],"2)":[101],"To":[102],"ensure":[103],"our":[104,141],"valid,":[107],"enforce":[109],"constraints":[112],"by":[113],"refining":[114],"initial":[116],"graph":[117],"outputs.":[119],"3)":[120],"Monte":[122],"Carlo":[123],"tree":[124],"search":[125],"(MCTS)":[126],"method":[127],"further":[128],"optimizes":[129],"logic":[131],"redundancy":[132],"generated":[135],"graph.":[136],"Experimental":[137],"results":[138],"demonstrate":[139],"that":[140],"proposed":[142],"SynCircuit":[143],"can":[144],"more":[146],"realistic":[147],"and":[150],"enhance":[151],"ML":[152],"performance":[154],"downstream":[156],"tasks.":[159]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2026-04-09T08:11:56.329763","created_date":"2025-10-10T00:00:00"}
