{"id":"https://openalex.org/W2080566549","doi":"https://doi.org/10.1109/cscwd.2008.4537128","title":"Integrated ISS and FPGA SoC HW/SW Co-verification Environment Design","display_name":"Integrated ISS and FPGA SoC HW/SW Co-verification Environment Design","publication_year":2008,"publication_date":"2008-04-01","ids":{"openalex":"https://openalex.org/W2080566549","doi":"https://doi.org/10.1109/cscwd.2008.4537128","mag":"2080566549"},"language":"en","primary_location":{"id":"doi:10.1109/cscwd.2008.4537128","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cscwd.2008.4537128","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 12th International Conference on Computer Supported Cooperative Work in Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047778456","display_name":"Xunying Zhang","orcid":"https://orcid.org/0009-0009-2242-9565"},"institutions":[{"id":"https://openalex.org/I4210089056","display_name":"Beijing Microelectronics Technology Institute","ror":"https://ror.org/007y7ej30","country_code":"CN","type":"other","lineage":["https://openalex.org/I4210089056"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Xunying Zhang","raw_affiliation_strings":["Xi''an Microelectronics Technology Institute, Xi'an, China","Xian Microelectron. Technol. Inst., Xian"],"affiliations":[{"raw_affiliation_string":"Xi''an Microelectronics Technology Institute, Xi'an, China","institution_ids":["https://openalex.org/I4210089056"]},{"raw_affiliation_string":"Xian Microelectron. Technol. Inst., Xian","institution_ids":["https://openalex.org/I4210089056"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026820022","display_name":"Hui Fei","orcid":"https://orcid.org/0000-0003-0861-6021"},"institutions":[{"id":"https://openalex.org/I4210089056","display_name":"Beijing Microelectronics Technology Institute","ror":"https://ror.org/007y7ej30","country_code":"CN","type":"other","lineage":["https://openalex.org/I4210089056"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Fei Hui","raw_affiliation_strings":["Xi''an Microelectronics Technology Institute, Xi'an, China","Xi\u00bfan Microelectronics Technology Institute, China"],"affiliations":[{"raw_affiliation_string":"Xi''an Microelectronics Technology Institute, Xi'an, China","institution_ids":["https://openalex.org/I4210089056"]},{"raw_affiliation_string":"Xi\u00bfan Microelectronics Technology Institute, China","institution_ids":["https://openalex.org/I4210089056"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100367009","display_name":"Qiang Wang","orcid":"https://orcid.org/0000-0002-7078-7545"},"institutions":[{"id":"https://openalex.org/I4210089056","display_name":"Beijing Microelectronics Technology Institute","ror":"https://ror.org/007y7ej30","country_code":"CN","type":"other","lineage":["https://openalex.org/I4210089056"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qiang Wang","raw_affiliation_strings":["Xi''an Microelectronics Technology Institute, Xi'an, China","Xi\u00bfan Microelectronics Technology Institute, China"],"affiliations":[{"raw_affiliation_string":"Xi''an Microelectronics Technology Institute, Xi'an, China","institution_ids":["https://openalex.org/I4210089056"]},{"raw_affiliation_string":"Xi\u00bfan Microelectronics Technology Institute, China","institution_ids":["https://openalex.org/I4210089056"]}]},{"author_position":"last","author":{"id":null,"display_name":"Xubang Shen","orcid":null},"institutions":[{"id":"https://openalex.org/I4210089056","display_name":"Beijing Microelectronics Technology Institute","ror":"https://ror.org/007y7ej30","country_code":"CN","type":"other","lineage":["https://openalex.org/I4210089056"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xubang Shen","raw_affiliation_strings":["Xi''an Microelectronics Technology Institute, Xi'an, China","Xi\u00bfan Microelectronics Technology Institute, China"],"affiliations":[{"raw_affiliation_string":"Xi''an Microelectronics Technology Institute, Xi'an, China","institution_ids":["https://openalex.org/I4210089056"]},{"raw_affiliation_string":"Xi\u00bfan Microelectronics Technology Institute, China","institution_ids":["https://openalex.org/I4210089056"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5047778456"],"corresponding_institution_ids":["https://openalex.org/I4210089056"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.08302485,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1071","last_page":"1075"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.829415500164032},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.7554405927658081},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6705566644668579},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.5603383779525757},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.557108461856842},{"id":"https://openalex.org/keywords/debugger","display_name":"Debugger","score":0.5404345393180847},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4447479844093323},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.44084370136260986},{"id":"https://openalex.org/keywords/protocol","display_name":"Protocol (science)","score":0.427828311920166},{"id":"https://openalex.org/keywords/component","display_name":"Component (thermodynamics)","score":0.4119328260421753},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.30204057693481445},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.18550243973731995}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.829415500164032},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7554405927658081},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6705566644668579},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.5603383779525757},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.557108461856842},{"id":"https://openalex.org/C2778485113","wikidata":"https://www.wikidata.org/wiki/Q193231","display_name":"Debugger","level":3,"score":0.5404345393180847},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4447479844093323},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.44084370136260986},{"id":"https://openalex.org/C2780385302","wikidata":"https://www.wikidata.org/wiki/Q367158","display_name":"Protocol (science)","level":3,"score":0.427828311920166},{"id":"https://openalex.org/C168167062","wikidata":"https://www.wikidata.org/wiki/Q1117970","display_name":"Component (thermodynamics)","level":2,"score":0.4119328260421753},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.30204057693481445},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.18550243973731995},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C71924100","wikidata":"https://www.wikidata.org/wiki/Q11190","display_name":"Medicine","level":0,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C142724271","wikidata":"https://www.wikidata.org/wiki/Q7208","display_name":"Pathology","level":1,"score":0.0},{"id":"https://openalex.org/C204787440","wikidata":"https://www.wikidata.org/wiki/Q188504","display_name":"Alternative medicine","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cscwd.2008.4537128","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cscwd.2008.4537128","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 12th International Conference on Computer Supported Cooperative Work in Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1541510538","https://openalex.org/W2086053354","https://openalex.org/W2101896481","https://openalex.org/W2120496971","https://openalex.org/W2164933241","https://openalex.org/W2169782229","https://openalex.org/W4244857419","https://openalex.org/W4252242593","https://openalex.org/W6675393038"],"related_works":["https://openalex.org/W2800641345","https://openalex.org/W2886673879","https://openalex.org/W564953056","https://openalex.org/W2061184006","https://openalex.org/W2381239448","https://openalex.org/W4236910510","https://openalex.org/W2092932442","https://openalex.org/W2543963479","https://openalex.org/W1751798423","https://openalex.org/W2993910401"],"abstract_inverted_index":{"This":[0],"paper":[1],"developed":[2],"an":[3,32],"integrated":[4],"ISS":[5,33,50],"and":[6,17,21,51],"FPGA":[7,46,52],"SoC":[8,88],"co-verification":[9,86],"platform":[10],"named":[11],"MLCV,":[12,20],"introduced":[13],"the":[14,37,45,62,65,77,85,96],"overall":[15],"structure":[16],"principle":[18],"of":[19,26],"described":[22],"each":[23],"component's":[24],"function":[25],"MLCV.":[27],"Processor":[28],"is":[29,53,69,82,93],"modeled":[30],"by":[31,55,84,91,95],"that":[34],"interface":[35],"with":[36],"source-level":[38],"debugger.":[39],"The":[40],"peripherals":[41],"are":[42],"implemented":[43,70],"in":[44,71],"board.":[47],"Communication":[48],"between":[49],"encapsulated":[54],"a":[56,74],"co-":[57],"verification":[58],"wrapper.":[59,87],"To":[60],"synchronize":[61],"bus":[63,67,75,99],"operation,":[64],"on-chip":[66],"protocol":[68],"FPGA.":[72],"As":[73],"master,":[76],"ISS's":[78],"peripheral":[79],"access":[80],"information":[81],"generated":[83],"architecture":[89],"supported":[90],"MLCV":[92],"limited":[94],"on-":[97],"chip":[98],"protocol.":[100]},"counts_by_year":[],"updated_date":"2026-04-16T08:26:57.006410","created_date":"2025-10-10T00:00:00"}