{"id":"https://openalex.org/W1672904416","doi":"https://doi.org/10.1109/cicc.1999.777249","title":"Intellectual property re-use and system emulation the keys to succeed the SoC challenge: a digital TV application","display_name":"Intellectual property re-use and system emulation the keys to succeed the SoC challenge: a digital TV application","publication_year":2003,"publication_date":"2003-01-20","ids":{"openalex":"https://openalex.org/W1672904416","doi":"https://doi.org/10.1109/cicc.1999.777249","mag":"1672904416"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.1999.777249","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.1999.777249","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5052044541","display_name":"G. Bollano","orcid":null},"institutions":[{"id":"https://openalex.org/I1298633626","display_name":"Telecom Italia Lab","ror":"https://ror.org/01rt74q71","country_code":"IT","type":"facility","lineage":["https://openalex.org/I1298633626","https://openalex.org/I137543953"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"G. Bollano","raw_affiliation_strings":["CSELT, Torino, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CSELT, Torino, Italy","institution_ids":["https://openalex.org/I1298633626"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034408489","display_name":"S. Claretto","orcid":null},"institutions":[{"id":"https://openalex.org/I1298633626","display_name":"Telecom Italia Lab","ror":"https://ror.org/01rt74q71","country_code":"IT","type":"facility","lineage":["https://openalex.org/I1298633626","https://openalex.org/I137543953"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"S. Claretto","raw_affiliation_strings":["CSELT, Torino, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CSELT, Torino, Italy","institution_ids":["https://openalex.org/I1298633626"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069170032","display_name":"L. Licciardi","orcid":null},"institutions":[{"id":"https://openalex.org/I1298633626","display_name":"Telecom Italia Lab","ror":"https://ror.org/01rt74q71","country_code":"IT","type":"facility","lineage":["https://openalex.org/I1298633626","https://openalex.org/I137543953"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"L. Licciardi","raw_affiliation_strings":["CSELT, Torino, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CSELT, Torino, Italy","institution_ids":["https://openalex.org/I1298633626"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033861663","display_name":"A. Montanaro","orcid":null},"institutions":[{"id":"https://openalex.org/I1298633626","display_name":"Telecom Italia Lab","ror":"https://ror.org/01rt74q71","country_code":"IT","type":"facility","lineage":["https://openalex.org/I1298633626","https://openalex.org/I137543953"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"A. Montanaro","raw_affiliation_strings":["CSELT, Torino, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CSELT, Torino, Italy","institution_ids":["https://openalex.org/I1298633626"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070332755","display_name":"L. Pilati","orcid":null},"institutions":[{"id":"https://openalex.org/I1298633626","display_name":"Telecom Italia Lab","ror":"https://ror.org/01rt74q71","country_code":"IT","type":"facility","lineage":["https://openalex.org/I1298633626","https://openalex.org/I137543953"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"L. Pilati","raw_affiliation_strings":["CSELT, Torino, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CSELT, Torino, Italy","institution_ids":["https://openalex.org/I1298633626"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5035428230","display_name":"M. Turolla","orcid":null},"institutions":[{"id":"https://openalex.org/I1298633626","display_name":"Telecom Italia Lab","ror":"https://ror.org/01rt74q71","country_code":"IT","type":"facility","lineage":["https://openalex.org/I1298633626","https://openalex.org/I137543953"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Turolla","raw_affiliation_strings":["CSELT, Torino, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CSELT, Torino, Italy","institution_ids":["https://openalex.org/I1298633626"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1298633626"],"apc_list":null,"apc_paid":null,"fwci":0.4649,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.57065076,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"91","last_page":"94"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.865696132183075},{"id":"https://openalex.org/keywords/hardware-emulation","display_name":"Hardware emulation","score":0.6730420589447021},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.639865517616272},{"id":"https://openalex.org/keywords/interoperability","display_name":"Interoperability","score":0.6293967366218567},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5806936621665955},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5663094520568848},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.49060383439064026},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.4679017961025238},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.43772563338279724},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.43584197759628296},{"id":"https://openalex.org/keywords/intellectual-property","display_name":"Intellectual property","score":0.42310231924057007},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.41036856174468994},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.3219255208969116},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.23968270421028137},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.19027665257453918}],"concepts":[{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.865696132183075},{"id":"https://openalex.org/C94115699","wikidata":"https://www.wikidata.org/wiki/Q5656406","display_name":"Hardware emulation","level":3,"score":0.6730420589447021},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.639865517616272},{"id":"https://openalex.org/C20136886","wikidata":"https://www.wikidata.org/wiki/Q749647","display_name":"Interoperability","level":2,"score":0.6293967366218567},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5806936621665955},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5663094520568848},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.49060383439064026},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.4679017961025238},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.43772563338279724},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.43584197759628296},{"id":"https://openalex.org/C34974158","wikidata":"https://www.wikidata.org/wiki/Q131257","display_name":"Intellectual property","level":2,"score":0.42310231924057007},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.41036856174468994},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.3219255208969116},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.23968270421028137},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.19027665257453918},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc.1999.777249","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.1999.777249","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6499999761581421,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W1501425349","https://openalex.org/W2115312095"],"related_works":["https://openalex.org/W1869168044","https://openalex.org/W2103996454","https://openalex.org/W3029775214","https://openalex.org/W2390650884","https://openalex.org/W2093057572","https://openalex.org/W2132158385","https://openalex.org/W2129151116","https://openalex.org/W2170071008","https://openalex.org/W2001552871","https://openalex.org/W1974143443"],"abstract_inverted_index":{"In":[0],"the":[1,13,56,72,81,89,104,110],"ICT":[2],"(Information":[3],"and":[4,12,18,30,117],"Communication":[5],"Technologies)":[6],"scenario":[7],"service":[8],"evaluation,":[9],"standard":[10],"stabilization":[11],"concurrent":[14],"development":[15,74],"of":[16],"hardware":[17],"software":[19],"are":[20],"key":[21],"elements":[22],"to":[23,36,88],"design":[24,106],"innovative":[25],"systems.":[26],"Emulation,":[27],"fast":[28,78],"prototyping":[29],"IP":[31],"re-use":[32],"can":[33],"really":[34],"help":[35],"obtain":[37],"time-to":[38],"market":[39],"solutions.":[40],"The":[41,69],"papers":[42],"deals":[43],"with":[44],"an":[45,85],"industrial":[46],"MPEG/ATM":[47],"remultiplexing":[48],"equipment":[49],"(REMUX)":[50],"for":[51,63],"digital":[52,59],"TV":[53],"applications":[54],"in":[55],"SDVB":[57],"(switched":[58],"video":[60],"broadcast)":[61],"area":[62],"either":[64],"satellite":[65],"or":[66],"cable":[67],"distribution.":[68],"paper":[70],"reports":[71],"REMUX":[73],"cycle":[75],"highlighting":[76],"its":[77],"evolution":[79],"from":[80],"prototype":[82],"based":[83,108],"on":[84,91,103,109],"embedded":[86],"system":[87,118],"System":[90],"Chip":[92],"realization":[93],"(0.25":[94],"/spl":[95],"mu/m,":[96],"ST":[97],"Microelectronics":[98],"CMOS":[99],"technology),":[100],"mainly":[101],"focusing":[102],"effective":[105],"methodology":[107],"CSELT":[111],"intellectual":[112],"property":[113],"library":[114],"(VIP/sup":[115],"TM/)":[116],"emulation.":[119]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}