{"id":"https://openalex.org/W3005505898","doi":"https://doi.org/10.1109/asicon47005.2019.8983453","title":"A High-speed Dynamic Domino Full Adder Based on DICG Positive Feedback","display_name":"A High-speed Dynamic Domino Full Adder Based on DICG Positive Feedback","publication_year":2019,"publication_date":"2019-10-01","ids":{"openalex":"https://openalex.org/W3005505898","doi":"https://doi.org/10.1109/asicon47005.2019.8983453","mag":"3005505898"},"language":"en","primary_location":{"id":"doi:10.1109/asicon47005.2019.8983453","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon47005.2019.8983453","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE 13th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100390603","display_name":"Xiaotian Zhang","orcid":"https://orcid.org/0000-0003-4112-546X"},"institutions":[{"id":"https://openalex.org/I109935558","display_name":"Ningbo University","ror":"https://ror.org/03et85d35","country_code":"CN","type":"education","lineage":["https://openalex.org/I109935558"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Xiaotian Zhang","raw_affiliation_strings":["Faculty of Electrical Engineering and Computer Science, Ningbo University,Ningbo,China,315211","Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo, China"],"affiliations":[{"raw_affiliation_string":"Faculty of Electrical Engineering and Computer Science, Ningbo University,Ningbo,China,315211","institution_ids":["https://openalex.org/I109935558"]},{"raw_affiliation_string":"Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo, China","institution_ids":["https://openalex.org/I109935558"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5106892182","display_name":"Pengjun Wang","orcid":"https://orcid.org/0000-0002-1461-3719"},"institutions":[{"id":"https://openalex.org/I146620803","display_name":"Wenzhou University","ror":"https://ror.org/020hxh324","country_code":"CN","type":"education","lineage":["https://openalex.org/I146620803"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Pengjun Wang","raw_affiliation_strings":["College of Electrical and Electronic Engineering, Wenzhou University,Wenzhou,China,325035","College of Electrical and Electronic Engineering, Wenzhou University, Wenzhou, China"],"affiliations":[{"raw_affiliation_string":"College of Electrical and Electronic Engineering, Wenzhou University,Wenzhou,China,325035","institution_ids":["https://openalex.org/I146620803"]},{"raw_affiliation_string":"College of Electrical and Electronic Engineering, Wenzhou University, Wenzhou, China","institution_ids":["https://openalex.org/I146620803"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101976074","display_name":"Yunfei Yu","orcid":null},"institutions":[{"id":"https://openalex.org/I109935558","display_name":"Ningbo University","ror":"https://ror.org/03et85d35","country_code":"CN","type":"education","lineage":["https://openalex.org/I109935558"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yunfei Yu","raw_affiliation_strings":["Faculty of Electrical Engineering and Computer Science, Ningbo University,Ningbo,China,315211","Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo, China"],"affiliations":[{"raw_affiliation_string":"Faculty of Electrical Engineering and Computer Science, Ningbo University,Ningbo,China,315211","institution_ids":["https://openalex.org/I109935558"]},{"raw_affiliation_string":"Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo, China","institution_ids":["https://openalex.org/I109935558"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108046742","display_name":"Yuejun Zhang","orcid":"https://orcid.org/0000-0003-1132-6332"},"institutions":[{"id":"https://openalex.org/I4210132990","display_name":"State Key Laboratory of Cryptology","ror":"https://ror.org/02pn5rj08","country_code":"CN","type":"government","lineage":["https://openalex.org/I4210132990"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuejun Zhang","raw_affiliation_strings":["State Key Laboratory of Cryptology,P. O. Box 5159, Beijing,China,100878","State Key Laboratory of Cryptology, P. O. Box 5159, Beijing, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Cryptology,P. O. Box 5159, Beijing,China,100878","institution_ids":["https://openalex.org/I4210132990"]},{"raw_affiliation_string":"State Key Laboratory of Cryptology, P. O. Box 5159, Beijing, China","institution_ids":["https://openalex.org/I4210132990"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5083851173","display_name":"Shunxin Ye","orcid":null},"institutions":[{"id":"https://openalex.org/I109935558","display_name":"Ningbo University","ror":"https://ror.org/03et85d35","country_code":"CN","type":"education","lineage":["https://openalex.org/I109935558"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shunxin Ye","raw_affiliation_strings":["Faculty of Electrical Engineering and Computer Science, Ningbo University,Ningbo,China,315211","Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo, China"],"affiliations":[{"raw_affiliation_string":"Faculty of Electrical Engineering and Computer Science, Ningbo University,Ningbo,China,315211","institution_ids":["https://openalex.org/I109935558"]},{"raw_affiliation_string":"Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo, China","institution_ids":["https://openalex.org/I109935558"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5100390603"],"corresponding_institution_ids":["https://openalex.org/I109935558"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.17117312,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8319443464279175},{"id":"https://openalex.org/keywords/domino","display_name":"Domino","score":0.7873963713645935},{"id":"https://openalex.org/keywords/domino-logic","display_name":"Domino logic","score":0.7251993417739868},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6688058972358704},{"id":"https://openalex.org/keywords/power\u2013delay-product","display_name":"Power\u2013delay product","score":0.5717642307281494},{"id":"https://openalex.org/keywords/dynamic-demand","display_name":"Dynamic demand","score":0.564534604549408},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5631632804870605},{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.44496703147888184},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.42545557022094727},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3197539448738098},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2833024859428406},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.27866223454475403},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.272392213344574},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.2512872517108917},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21520140767097473},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.12744438648223877},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.09690874814987183}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8319443464279175},{"id":"https://openalex.org/C2776416436","wikidata":"https://www.wikidata.org/wiki/Q3751781","display_name":"Domino","level":3,"score":0.7873963713645935},{"id":"https://openalex.org/C2777555262","wikidata":"https://www.wikidata.org/wiki/Q173391","display_name":"Domino logic","level":5,"score":0.7251993417739868},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6688058972358704},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.5717642307281494},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.564534604549408},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5631632804870605},{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.44496703147888184},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.42545557022094727},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3197539448738098},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2833024859428406},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.27866223454475403},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.272392213344574},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.2512872517108917},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21520140767097473},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.12744438648223877},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.09690874814987183},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C161790260","wikidata":"https://www.wikidata.org/wiki/Q82264","display_name":"Catalysis","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon47005.2019.8983453","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon47005.2019.8983453","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE 13th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8700000047683716,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1974524309","https://openalex.org/W2008128918","https://openalex.org/W2169957452","https://openalex.org/W2537705861","https://openalex.org/W2755618956","https://openalex.org/W2793767356","https://openalex.org/W2913719236"],"related_works":["https://openalex.org/W4231158717","https://openalex.org/W2059009651","https://openalex.org/W3174071739","https://openalex.org/W4254482168","https://openalex.org/W18274992","https://openalex.org/W2098328611","https://openalex.org/W2100009051","https://openalex.org/W2150513440","https://openalex.org/W4387736942","https://openalex.org/W2039862733"],"abstract_inverted_index":{"Dynamic":[0],"domino":[1,40,84],"circuit":[2,19,41,75],"affords":[3],"significant":[4],"advantages":[5],"in":[6,70,89,95],"speed":[7,90],"performance":[8,91],"and":[9,17,27,63,74,92],"area":[10],"by":[11,44],"virtue":[12],"of":[13],"dynamic":[14,39,83],"operating":[15],"behavior":[16],"un-complementary":[18],"structure,":[20],"while":[21],"compromising":[22],"too":[23],"much":[24],"power":[25,72],"consumption":[26],"noise":[28],"tolerance.":[29],"In":[30],"this":[31],"paper,":[32],"a":[33,104],"highspeed":[34],"full":[35],"adder":[36,85],"based":[37],"on":[38],"is":[42],"proposed":[43],"utilizing":[45],"the":[46,54,59,81],"DICG":[47,55],"(Delayed-Inverted-CLK-Gating)":[48],"positive":[49],"feedback":[50],"scheme.":[51],"Thanks":[52],"to":[53],"technique,":[56],"it":[57],"relaxes":[58],"competition":[60],"between":[61],"pull-up":[62],"pull-down":[64],"networks":[65],"effectively,":[66],"achieving":[67],"notable":[68],"improvements":[69],"speed,":[71],"dissipation":[73],"stability.":[76],"Experimental":[77],"results":[78],"show":[79],"that":[80],"presented":[82],"exhibits":[86],"21.2%":[87],"improvement":[88],"18.7%":[93],"reduction":[94],"power-delay":[96],"product":[97],"compared":[98],"with":[99],"previous":[100],"work":[101],"when":[102],"using":[103],"TSMC":[105],"65nm":[106],"process":[107],"technology.":[108]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
