{"id":"https://openalex.org/W2038698682","doi":"https://doi.org/10.1109/asicon.2011.6157315","title":"Design of a reconfigurable network interface processor","display_name":"Design of a reconfigurable network interface processor","publication_year":2011,"publication_date":"2011-10-01","ids":{"openalex":"https://openalex.org/W2038698682","doi":"https://doi.org/10.1109/asicon.2011.6157315","mag":"2038698682"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2011.6157315","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157315","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100603174","display_name":"Lei Zhang","orcid":"https://orcid.org/0009-0005-9977-283X"},"institutions":[{"id":"https://openalex.org/I4210136859","display_name":"Xi\u2019an University of Posts and Telecommunications","ror":"https://ror.org/04jn0td46","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210136859"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Lei Zhang","raw_affiliation_strings":["College of Electronic Engineering, Xi'an University of Posts and Telecommunications, Xi'an, China","College of Electronic Engineering Xi'An University of Posts and Telecom, 710061, China"],"affiliations":[{"raw_affiliation_string":"College of Electronic Engineering, Xi'an University of Posts and Telecommunications, Xi'an, China","institution_ids":["https://openalex.org/I4210136859"]},{"raw_affiliation_string":"College of Electronic Engineering Xi'An University of Posts and Telecom, 710061, China","institution_ids":["https://openalex.org/I4210136859"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100455297","display_name":"Tao Li","orcid":"https://orcid.org/0000-0002-3337-6202"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Tao Li","raw_affiliation_strings":["Shaanxi Provincial Research Center of Telecom ASIC Design, Xi'an, China","Shaanxi Provincial Research Center of Telecom ASIC Design, Xi'An, 710061, China"],"affiliations":[{"raw_affiliation_string":"Shaanxi Provincial Research Center of Telecom ASIC Design, Xi'an, China","institution_ids":[]},{"raw_affiliation_string":"Shaanxi Provincial Research Center of Telecom ASIC Design, Xi'An, 710061, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101926349","display_name":"Zhentao Li","orcid":"https://orcid.org/0000-0001-7178-033X"},"institutions":[{"id":"https://openalex.org/I4210136859","display_name":"Xi\u2019an University of Posts and Telecommunications","ror":"https://ror.org/04jn0td46","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210136859"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhentao Li","raw_affiliation_strings":["College of Electronic Engineering, Xi'an University of Posts and Telecommunications, Xi'an, China","College of Electronic Engineering Xi'An University of Posts and Telecom, 710061, China"],"affiliations":[{"raw_affiliation_string":"College of Electronic Engineering, Xi'an University of Posts and Telecommunications, Xi'an, China","institution_ids":["https://openalex.org/I4210136859"]},{"raw_affiliation_string":"College of Electronic Engineering Xi'An University of Posts and Telecom, 710061, China","institution_ids":["https://openalex.org/I4210136859"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100514186","display_name":"Lin Jiang","orcid":"https://orcid.org/0009-0004-3725-7739"},"institutions":[{"id":"https://openalex.org/I4210136859","display_name":"Xi\u2019an University of Posts and Telecommunications","ror":"https://ror.org/04jn0td46","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210136859"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lin Jiang","raw_affiliation_strings":["College of Electronic Engineering, Xi'an University of Posts and Telecommunications, Xi'an, China","College of Electronic Engineering Xi'An University of Posts and Telecom, 710061, China"],"affiliations":[{"raw_affiliation_string":"College of Electronic Engineering, Xi'an University of Posts and Telecommunications, Xi'an, China","institution_ids":["https://openalex.org/I4210136859"]},{"raw_affiliation_string":"College of Electronic Engineering Xi'An University of Posts and Telecom, 710061, China","institution_ids":["https://openalex.org/I4210136859"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5100603174"],"corresponding_institution_ids":["https://openalex.org/I4210136859"],"apc_list":null,"apc_paid":null,"fwci":0.2519,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.54662594,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"zi","issue":null,"first_page":"755","last_page":"759"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9908999800682068,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9908999800682068,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.989799976348877,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14470","display_name":"Advanced Data Processing Techniques","score":0.9635999798774719,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7681645154953003},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.730247974395752},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.6990038752555847},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.589755117893219},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.5492461323738098},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.543825626373291},{"id":"https://openalex.org/keywords/network-processor","display_name":"Network processor","score":0.49650436639785767},{"id":"https://openalex.org/keywords/network-interface","display_name":"Network interface","score":0.4945041835308075},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4705244302749634},{"id":"https://openalex.org/keywords/convergence","display_name":"Convergence (economics)","score":0.4612198770046234},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4274805188179016},{"id":"https://openalex.org/keywords/layer","display_name":"Layer (electronics)","score":0.4171483516693115},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3039264678955078},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.29527515172958374},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.11761102080345154},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.07473397254943848}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7681645154953003},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.730247974395752},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.6990038752555847},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.589755117893219},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.5492461323738098},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.543825626373291},{"id":"https://openalex.org/C74366991","wikidata":"https://www.wikidata.org/wiki/Q2755335","display_name":"Network processor","level":3,"score":0.49650436639785767},{"id":"https://openalex.org/C103987645","wikidata":"https://www.wikidata.org/wiki/Q985806","display_name":"Network interface","level":3,"score":0.4945041835308075},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4705244302749634},{"id":"https://openalex.org/C2777303404","wikidata":"https://www.wikidata.org/wiki/Q759757","display_name":"Convergence (economics)","level":2,"score":0.4612198770046234},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4274805188179016},{"id":"https://openalex.org/C2779227376","wikidata":"https://www.wikidata.org/wiki/Q6505497","display_name":"Layer (electronics)","level":2,"score":0.4171483516693115},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3039264678955078},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.29527515172958374},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.11761102080345154},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.07473397254943848},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C172173386","wikidata":"https://www.wikidata.org/wiki/Q79984","display_name":"Ethernet","level":2,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C178790620","wikidata":"https://www.wikidata.org/wiki/Q11351","display_name":"Organic chemistry","level":1,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2011.6157315","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157315","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2914607376","https://openalex.org/W2249714048","https://openalex.org/W1971358294","https://openalex.org/W2156440845","https://openalex.org/W4245232836","https://openalex.org/W1501464578","https://openalex.org/W2022588050","https://openalex.org/W643312261","https://openalex.org/W4239973724","https://openalex.org/W4239934115"],"abstract_inverted_index":{"A":[0,29],"reconfigurable":[1],"architecture":[2],"for":[3,45],"networking":[4],"equipment":[5],"interface":[6],"is":[7,11,17,35,42],"proposed.":[8],"This":[9,40],"processor":[10,41],"field":[12],"programmable":[13],"and":[14],"its":[15],"implementation":[16],"based":[18],"on":[19,47],"a":[20],"model":[21],"of":[22,32],"arithmetic":[23],"augmented":[24],"finite":[25],"state":[26],"machine":[27],"(AFSM).":[28],"structured":[30],"realization":[31],"the":[33,38,52],"AFSM":[34],"presented":[36],"in":[37],"paper.":[39],"specially":[43],"designed":[44],"interfaces":[46],"low":[48],"layers,":[49],"such":[50],"as":[51],"physical":[53],"convergence":[54],"layer.":[55]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}