{"id":"https://openalex.org/W2059605133","doi":"https://doi.org/10.1109/asicon.2011.6157207","title":"CPIPQ: A common platform for silicon IP qualification","display_name":"CPIPQ: A common platform for silicon IP qualification","publication_year":2011,"publication_date":"2011-10-01","ids":{"openalex":"https://openalex.org/W2059605133","doi":"https://doi.org/10.1109/asicon.2011.6157207","mag":"2059605133"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2011.6157207","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157207","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5076267588","display_name":"Mark Ping Chan Mok","orcid":null},"institutions":[{"id":"https://openalex.org/I146617529","display_name":"Applied Science and Technology Research Institute","ror":"https://ror.org/03xmkea05","country_code":"CN","type":"facility","lineage":["https://openalex.org/I146617529"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Mark P. C. Mok","raw_affiliation_strings":["IC Design Group, Hong Kong Applied Science and Technology Research Institute, Hong Kong, China","IC Design Group, Hong Kong Applied Science and Technology Research Institute (ASTRI), Hong Kong"],"affiliations":[{"raw_affiliation_string":"IC Design Group, Hong Kong Applied Science and Technology Research Institute, Hong Kong, China","institution_ids":["https://openalex.org/I146617529"]},{"raw_affiliation_string":"IC Design Group, Hong Kong Applied Science and Technology Research Institute (ASTRI), Hong Kong","institution_ids":["https://openalex.org/I146617529"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047295554","display_name":"Kenneth C. K. Lo","orcid":null},"institutions":[{"id":"https://openalex.org/I146617529","display_name":"Applied Science and Technology Research Institute","ror":"https://ror.org/03xmkea05","country_code":"CN","type":"facility","lineage":["https://openalex.org/I146617529"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Kenneth C. K. Lo","raw_affiliation_strings":["IC Design Group, Hong Kong Applied Science and Technology Research Institute, Hong Kong, China","IC Design Group, Hong Kong Applied Science and Technology Research Institute (ASTRI), Hong Kong"],"affiliations":[{"raw_affiliation_string":"IC Design Group, Hong Kong Applied Science and Technology Research Institute, Hong Kong, China","institution_ids":["https://openalex.org/I146617529"]},{"raw_affiliation_string":"IC Design Group, Hong Kong Applied Science and Technology Research Institute (ASTRI), Hong Kong","institution_ids":["https://openalex.org/I146617529"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073565712","display_name":"Yuzhong Jiao","orcid":null},"institutions":[{"id":"https://openalex.org/I146617529","display_name":"Applied Science and Technology Research Institute","ror":"https://ror.org/03xmkea05","country_code":"CN","type":"facility","lineage":["https://openalex.org/I146617529"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuzhong Jiao","raw_affiliation_strings":["IC Design Group, Hong Kong Applied Science and Technology Research Institute, Hong Kong, China","IC Design Group, Hong Kong Applied Science and Technology Research Institute (ASTRI), Hong Kong"],"affiliations":[{"raw_affiliation_string":"IC Design Group, Hong Kong Applied Science and Technology Research Institute, Hong Kong, China","institution_ids":["https://openalex.org/I146617529"]},{"raw_affiliation_string":"IC Design Group, Hong Kong Applied Science and Technology Research Institute (ASTRI), Hong Kong","institution_ids":["https://openalex.org/I146617529"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5060245376","display_name":"Yiu Kei Li","orcid":null},"institutions":[{"id":"https://openalex.org/I146617529","display_name":"Applied Science and Technology Research Institute","ror":"https://ror.org/03xmkea05","country_code":"CN","type":"facility","lineage":["https://openalex.org/I146617529"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yiu Kei Li","raw_affiliation_strings":["IC Design Group, Hong Kong Applied Science and Technology Research Institute, Hong Kong, China","IC Design Group, Hong Kong Applied Science and Technology Research Institute (ASTRI), Hong Kong"],"affiliations":[{"raw_affiliation_string":"IC Design Group, Hong Kong Applied Science and Technology Research Institute, Hong Kong, China","institution_ids":["https://openalex.org/I146617529"]},{"raw_affiliation_string":"IC Design Group, Hong Kong Applied Science and Technology Research Institute (ASTRI), Hong Kong","institution_ids":["https://openalex.org/I146617529"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5076267588"],"corresponding_institution_ids":["https://openalex.org/I146617529"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.11176864,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"405","last_page":"408"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6345419883728027},{"id":"https://openalex.org/keywords/metric","display_name":"Metric (unit)","score":0.6278284192085266},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5469390153884888},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.49895334243774414},{"id":"https://openalex.org/keywords/intellectual-property","display_name":"Intellectual property","score":0.4888969957828522},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4676736295223236},{"id":"https://openalex.org/keywords/quality","display_name":"Quality (philosophy)","score":0.4622340798377991},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.45260539650917053},{"id":"https://openalex.org/keywords/ip-address-management","display_name":"IP address management","score":0.4499727487564087},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.42853209376335144},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.42785587906837463},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3768020570278168},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3543276786804199},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3047848045825958},{"id":"https://openalex.org/keywords/the-internet","display_name":"The Internet","score":0.27673599123954773},{"id":"https://openalex.org/keywords/internet-protocol","display_name":"Internet Protocol","score":0.179057776927948},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.16170352697372437}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6345419883728027},{"id":"https://openalex.org/C176217482","wikidata":"https://www.wikidata.org/wiki/Q860554","display_name":"Metric (unit)","level":2,"score":0.6278284192085266},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5469390153884888},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.49895334243774414},{"id":"https://openalex.org/C34974158","wikidata":"https://www.wikidata.org/wiki/Q131257","display_name":"Intellectual property","level":2,"score":0.4888969957828522},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4676736295223236},{"id":"https://openalex.org/C2779530757","wikidata":"https://www.wikidata.org/wiki/Q1207505","display_name":"Quality (philosophy)","level":2,"score":0.4622340798377991},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.45260539650917053},{"id":"https://openalex.org/C201980515","wikidata":"https://www.wikidata.org/wiki/Q13219707","display_name":"IP address management","level":4,"score":0.4499727487564087},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.42853209376335144},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.42785587906837463},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3768020570278168},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3543276786804199},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3047848045825958},{"id":"https://openalex.org/C110875604","wikidata":"https://www.wikidata.org/wiki/Q75","display_name":"The Internet","level":2,"score":0.27673599123954773},{"id":"https://openalex.org/C35341882","wikidata":"https://www.wikidata.org/wiki/Q8795","display_name":"Internet Protocol","level":3,"score":0.179057776927948},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.16170352697372437},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2011.6157207","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157207","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5600000023841858}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1986698883","https://openalex.org/W2042669502","https://openalex.org/W2126148497","https://openalex.org/W2142497484","https://openalex.org/W2157169083","https://openalex.org/W2532834788","https://openalex.org/W4243663926"],"related_works":["https://openalex.org/W2388040150","https://openalex.org/W4253195573","https://openalex.org/W2020934033","https://openalex.org/W63276784","https://openalex.org/W3011978806","https://openalex.org/W2002682434","https://openalex.org/W2059530328","https://openalex.org/W2156446048","https://openalex.org/W4230718388","https://openalex.org/W2047284788"],"abstract_inverted_index":{"With":[0],"the":[1,26,110],"increasing":[2],"complexity":[3],"of":[4,28,82,93,114],"system-on-chip":[5],"(SoC)":[6],"design,":[7],"intellectual":[8],"property":[9],"(IP)-based":[10],"design":[11,43],"flow":[12],"is":[13,74],"becoming":[14],"an":[15],"inevitable":[16],"trend":[17],"to":[18,55,76,85,108],"achieve":[19],"high":[20],"performance":[21],"and":[22,34,45,60,78,99],"short":[23],"time-to-market.":[24],"However":[25],"transfer":[27],"IP":[29,38,53,58,71,115],"core":[30],"remains":[31],"a":[32,67,80],"complex":[33],"time-consuming":[35],"process.":[36],"Different":[37],"vendors":[39],"usually":[40],"use":[41,104],"different":[42],"rules":[44],"tool":[46],"flows,":[47],"which":[48],"make":[49],"it":[50],"difficult":[51],"for":[52,70],"integrators":[54],"select":[56],"suitable":[57],"cores":[59],"integrate":[61],"them":[62],"rapidly.":[63],"In":[64],"this":[65],"paper,":[66],"common":[68,83],"platform":[69],"qualification":[72,94],"(CPIPQ)":[73],"presented":[75],"provide":[77],"establish":[79],"set":[81],"standards":[84],"qualify":[86],"Soft/Hard":[87],"IP.":[88],"There":[89],"are":[90,119],"two":[91],"kinds":[92],"methods:":[95],"subjective":[96,111],"quality":[97,101,112],"metric":[98],"objective":[100],"metric.":[102],"We":[103],"IEEE":[105],"QIP":[106],"Metric":[107],"evaluate":[109],"metrics":[113,118],"cores.":[116],"Objective":[117],"measured":[120],"automatically":[121],"by":[122,133],"using":[123],"commercial":[124],"EDA":[125],"tools,":[126],"as":[127,129],"well":[128],"tools":[130],"that":[131],"developed":[132],"ASTRI":[134],"IC":[135],"Design":[136],"Group.":[137]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
