{"id":"https://openalex.org/W2026858564","doi":"https://doi.org/10.1109/asicon.2011.6157204","title":"FPGA interconnect timing library based on the statistical method","display_name":"FPGA interconnect timing library based on the statistical method","publication_year":2011,"publication_date":"2011-10-01","ids":{"openalex":"https://openalex.org/W2026858564","doi":"https://doi.org/10.1109/asicon.2011.6157204","mag":"2026858564"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2011.6157204","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157204","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100851847","display_name":"Xiangzhi Meng","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Xiangzhi Meng","raw_affiliation_strings":["The State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","The State Key Lab of ASIC and System,Fudan University,Shanghai 201203,China)"],"affiliations":[{"raw_affiliation_string":"The State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"The State Key Lab of ASIC and System,Fudan University,Shanghai 201203,China)","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5107145124","display_name":"Liguang Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Liguang Chen","raw_affiliation_strings":["The State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","The State Key Lab of ASIC and System,Fudan University,Shanghai 201203,China)"],"affiliations":[{"raw_affiliation_string":"The State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"The State Key Lab of ASIC and System,Fudan University,Shanghai 201203,China)","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020063371","display_name":"Hao Zhou","orcid":"https://orcid.org/0009-0006-1673-5564"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hao Zhou","raw_affiliation_strings":["The State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","The State Key Lab of ASIC and System,Fudan University,Shanghai 201203,China)"],"affiliations":[{"raw_affiliation_string":"The State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"The State Key Lab of ASIC and System,Fudan University,Shanghai 201203,China)","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100370333","display_name":"Jian Wang","orcid":"https://orcid.org/0000-0001-5416-0649"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jian Wang","raw_affiliation_strings":["The State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","The State Key Lab of ASIC and System,Fudan University,Shanghai 201203,China)"],"affiliations":[{"raw_affiliation_string":"The State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"The State Key Lab of ASIC and System,Fudan University,Shanghai 201203,China)","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005595160","display_name":"Meng Yang","orcid":"https://orcid.org/0000-0003-2862-2015"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Meng Yang","raw_affiliation_strings":["The State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","The State Key Lab of ASIC and System,Fudan University,Shanghai 201203,China)"],"affiliations":[{"raw_affiliation_string":"The State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"The State Key Lab of ASIC and System,Fudan University,Shanghai 201203,China)","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081419061","display_name":"Jinmei Lai","orcid":"https://orcid.org/0009-0003-5238-4720"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jinmei Lai","raw_affiliation_strings":["The State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","The State Key Lab of ASIC and System,Fudan University,Shanghai 201203,China)"],"affiliations":[{"raw_affiliation_string":"The State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"The State Key Lab of ASIC and System,Fudan University,Shanghai 201203,China)","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5100851847"],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.2519,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.5429035,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"393","last_page":"396"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9952999949455261,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9952999949455261,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9890000224113464,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9876999855041504,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8270035982131958},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.8020743727684021},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7021582126617432},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.6648448705673218},{"id":"https://openalex.org/keywords/statistical-analysis","display_name":"Statistical analysis","score":0.4930567443370819},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4220009446144104},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3729906678199768},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.12148028612136841},{"id":"https://openalex.org/keywords/statistics","display_name":"Statistics","score":0.11753642559051514},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0854332447052002}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8270035982131958},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.8020743727684021},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7021582126617432},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.6648448705673218},{"id":"https://openalex.org/C2986587452","wikidata":"https://www.wikidata.org/wiki/Q938438","display_name":"Statistical analysis","level":2,"score":0.4930567443370819},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4220009446144104},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3729906678199768},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12148028612136841},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.11753642559051514},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0854332447052002}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2011.6157204","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157204","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W1984588379","https://openalex.org/W2030359186"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2155019192","https://openalex.org/W2014709025","https://openalex.org/W4200391368","https://openalex.org/W2355315220","https://openalex.org/W2210979487","https://openalex.org/W2074043759","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,21],"statistical":[4,34],"method":[5,35,45],"to":[6,54,59,77],"build":[7],"up":[8,53],"interconnect":[9,30],"timing":[10,14,31],"library":[11],"of":[12,24],"static":[13],"analysis":[15],"for":[16],"FPGA":[17,66],"design.":[18],"To":[19],"overcome":[20],"large":[22],"number":[23],"negative":[25],"values":[26],"in":[27],"the":[28,33,43,48,60,65,68],"traditional":[29],"library,":[32],"is":[36],"introduced.":[37],"The":[38],"experimental":[39],"results":[40,63],"show":[41],"that":[42],"proposed":[44],"could":[46],"improve":[47],"positive":[49],"ratio":[50],"and":[51],"achieve":[52],"22.35%":[55],"on":[56,64],"average.":[57],"Compared":[58],"tested":[61],"delay":[62,69],"chip,":[67],"error":[70],"rate":[71],"can":[72],"be":[73],"reduced":[74],"from":[75],"13.58%":[76],"11%.":[78]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}