{"id":"https://openalex.org/W2971976349","doi":"https://doi.org/10.1109/asap.2019.00011","title":"A Well-Equipped Implementation: Normal/Denormalized Half/Single/Double Precision IEEE 754 Floating-Point Adder/Subtracter","display_name":"A Well-Equipped Implementation: Normal/Denormalized Half/Single/Double Precision IEEE 754 Floating-Point Adder/Subtracter","publication_year":2019,"publication_date":"2019-07-01","ids":{"openalex":"https://openalex.org/W2971976349","doi":"https://doi.org/10.1109/asap.2019.00011","mag":"2971976349"},"language":"en","primary_location":{"id":"doi:10.1109/asap.2019.00011","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2019.00011","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048421422","display_name":"Brett Mathis","orcid":null},"institutions":[{"id":"https://openalex.org/I115475287","display_name":"Oklahoma State University","ror":"https://ror.org/01g9vbr38","country_code":"US","type":"education","lineage":["https://openalex.org/I115475287"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Brett Mathis","raw_affiliation_strings":["School of Electrical and Computer Engineering, Oklahoma State University, Stillwater, Oklahoma"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Oklahoma State University, Stillwater, Oklahoma","institution_ids":["https://openalex.org/I115475287"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033770307","display_name":"James E. Stine","orcid":"https://orcid.org/0000-0001-8767-390X"},"institutions":[{"id":"https://openalex.org/I115475287","display_name":"Oklahoma State University","ror":"https://ror.org/01g9vbr38","country_code":"US","type":"education","lineage":["https://openalex.org/I115475287"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"James E. Stine","raw_affiliation_strings":["School of Electrical and Computer Engineering, Oklahoma State University, Stillwater, Oklahoma"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Oklahoma State University, Stillwater, Oklahoma","institution_ids":["https://openalex.org/I115475287"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5048421422"],"corresponding_institution_ids":["https://openalex.org/I115475287"],"apc_list":null,"apc_paid":null,"fwci":0.0978,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.43390805,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"227","last_page":"234"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8355464935302734},{"id":"https://openalex.org/keywords/double-precision-floating-point-format","display_name":"Double-precision floating-point format","score":0.7521212100982666},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6530417799949646},{"id":"https://openalex.org/keywords/single-precision-floating-point-format","display_name":"Single-precision floating-point format","score":0.6221493482589722},{"id":"https://openalex.org/keywords/floating-point","display_name":"Floating point","score":0.4630228877067566},{"id":"https://openalex.org/keywords/point","display_name":"Point (geometry)","score":0.457851767539978},{"id":"https://openalex.org/keywords/ieee-floating-point","display_name":"IEEE floating point","score":0.4424353539943695},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3780338764190674},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.18539047241210938},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13743972778320312},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11164885759353638},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.06476190686225891}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8355464935302734},{"id":"https://openalex.org/C35912277","wikidata":"https://www.wikidata.org/wiki/Q1243369","display_name":"Double-precision floating-point format","level":3,"score":0.7521212100982666},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6530417799949646},{"id":"https://openalex.org/C133095886","wikidata":"https://www.wikidata.org/wiki/Q1307173","display_name":"Single-precision floating-point format","level":3,"score":0.6221493482589722},{"id":"https://openalex.org/C84211073","wikidata":"https://www.wikidata.org/wiki/Q117879","display_name":"Floating point","level":2,"score":0.4630228877067566},{"id":"https://openalex.org/C28719098","wikidata":"https://www.wikidata.org/wiki/Q44946","display_name":"Point (geometry)","level":2,"score":0.457851767539978},{"id":"https://openalex.org/C137231763","wikidata":"https://www.wikidata.org/wiki/Q828287","display_name":"IEEE floating point","level":3,"score":0.4424353539943695},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3780338764190674},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.18539047241210938},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13743972778320312},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11164885759353638},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.06476190686225891},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asap.2019.00011","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2019.00011","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320338294","display_name":"Air Force Research Laboratory","ror":"https://ror.org/02e2egq70"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W79353637","https://openalex.org/W1567646530","https://openalex.org/W1587217691","https://openalex.org/W2022042913","https://openalex.org/W2086189979","https://openalex.org/W2101906424","https://openalex.org/W2124020158","https://openalex.org/W2126762902","https://openalex.org/W2128700810","https://openalex.org/W2204310803","https://openalex.org/W2207050309","https://openalex.org/W2798490684","https://openalex.org/W6603201947"],"related_works":["https://openalex.org/W1564887326","https://openalex.org/W3215589575","https://openalex.org/W2587538765","https://openalex.org/W2000092506","https://openalex.org/W2596474508","https://openalex.org/W2169016399","https://openalex.org/W2730658480","https://openalex.org/W2116803521","https://openalex.org/W1573821047","https://openalex.org/W2565957982"],"abstract_inverted_index":{"This":[0,16,56,104],"paper":[1],"shows":[2],"the":[3,46,72,79,99],"implementation":[4],"and":[5,14,24,58,66,88,122],"design":[6,17,52,105],"of":[7,45,98],"a":[8,50,117],"completely":[9],"IEEE":[10,32,80,101],"754-compliant":[11],"floating-point":[12],"adder":[13,39,57],"subtracter.":[15],"focuses":[18],"on":[19],"maintaining":[20],"low":[21],"critical":[22],"delay":[23],"power,":[25],"while":[26],"still":[27],"containing":[28],"hardware":[29],"for":[30,63,85,110],"full":[31,61,108],"754":[33,81,102],"compliance.":[34],"A":[35],"novel":[36],"64-bit":[37],"prefix":[38],"structure":[40],"is":[41,90],"used,":[42],"where":[43],"most":[44],"performance":[47],"benefits":[48],"over":[49],"standard":[51],"come":[53],"from":[54],"parallelization.":[55],"subtracter":[59],"has":[60,71,107],"support":[62,109],"binary64,":[64,86],"binary32,":[65,87],"binary16":[67,89],"operands.":[68,112],"It":[69],"also":[70,106],"ability":[73],"to":[74,78],"convert":[75],"integer":[76],"values":[77],"standard.":[82],"Integer":[83],"conversion":[84,95],"supported,":[91],"as":[92,94],"well":[93],"between":[96],"any":[97],"aforementioned":[100],"precisions.":[103],"denormalized":[111],"Synthesis":[113],"results":[114],"presented":[115],"use":[116],"cmos32soi":[118],"32nm":[119],"CMOS":[120],"technology":[121],"ARM":[123],"standard-cells.":[124]},"counts_by_year":[{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
