{"id":"https://openalex.org/W2132257274","doi":"https://doi.org/10.1109/asap.2010.5540967","title":"Optimizing DDR-SDRAM communications at C-level for automatically-generated hardware accelerators an experience with the Altera C2H HLS tool","display_name":"Optimizing DDR-SDRAM communications at C-level for automatically-generated hardware accelerators an experience with the Altera C2H HLS tool","publication_year":2010,"publication_date":"2010-07-01","ids":{"openalex":"https://openalex.org/W2132257274","doi":"https://doi.org/10.1109/asap.2010.5540967","mag":"2132257274"},"language":"en","primary_location":{"id":"doi:10.1109/asap.2010.5540967","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2010.5540967","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://inria.hal.science/inria-00482035/document","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010785753","display_name":"Christophe Alias","orcid":"https://orcid.org/0000-0002-5387-2369"},"institutions":[{"id":"https://openalex.org/I100532134","display_name":"Universit\u00e9 Claude Bernard Lyon 1","ror":"https://ror.org/029brtt94","country_code":"FR","type":"education","lineage":["https://openalex.org/I100532134","https://openalex.org/I203339264"]},{"id":"https://openalex.org/I113428412","display_name":"\u00c9cole Normale Sup\u00e9rieure de Lyon","ror":"https://ror.org/04zmssz18","country_code":"FR","type":"education","lineage":["https://openalex.org/I113428412","https://openalex.org/I203339264"]},{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I1326498283","display_name":"Institut national de recherche en sciences et technologies du num\u00e9rique","ror":"https://ror.org/02kvxyf05","country_code":"FR","type":"government","lineage":["https://openalex.org/I1326498283"]},{"id":"https://openalex.org/I4210144566","display_name":"Laboratoire de l'Informatique du Parall\u00e9lisme","ror":"https://ror.org/04msnz457","country_code":"FR","type":"facility","lineage":["https://openalex.org/I100532134","https://openalex.org/I113428412","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I203339264","https://openalex.org/I203339264","https://openalex.org/I4210144566"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Christophe Alias","raw_affiliation_strings":["LIP,UMR 5668 CNRS-ENS Lyon, UCB Lyon-Inria, France","LIP, UMR 5668 CNRS \u2014 ENS Lyon \u2014 UCB Lyon \u2014 Inria, France"],"affiliations":[{"raw_affiliation_string":"LIP,UMR 5668 CNRS-ENS Lyon, UCB Lyon-Inria, France","institution_ids":["https://openalex.org/I113428412","https://openalex.org/I100532134","https://openalex.org/I1294671590"]},{"raw_affiliation_string":"LIP, UMR 5668 CNRS \u2014 ENS Lyon \u2014 UCB Lyon \u2014 Inria, France","institution_ids":["https://openalex.org/I4210144566","https://openalex.org/I100532134","https://openalex.org/I1326498283","https://openalex.org/I1294671590","https://openalex.org/I113428412"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058222450","display_name":"Alain Darte","orcid":null},"institutions":[{"id":"https://openalex.org/I100532134","display_name":"Universit\u00e9 Claude Bernard Lyon 1","ror":"https://ror.org/029brtt94","country_code":"FR","type":"education","lineage":["https://openalex.org/I100532134","https://openalex.org/I203339264"]},{"id":"https://openalex.org/I113428412","display_name":"\u00c9cole Normale Sup\u00e9rieure de Lyon","ror":"https://ror.org/04zmssz18","country_code":"FR","type":"education","lineage":["https://openalex.org/I113428412","https://openalex.org/I203339264"]},{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I1326498283","display_name":"Institut national de recherche en sciences et technologies du num\u00e9rique","ror":"https://ror.org/02kvxyf05","country_code":"FR","type":"government","lineage":["https://openalex.org/I1326498283"]},{"id":"https://openalex.org/I4210144566","display_name":"Laboratoire de l'Informatique du Parall\u00e9lisme","ror":"https://ror.org/04msnz457","country_code":"FR","type":"facility","lineage":["https://openalex.org/I100532134","https://openalex.org/I113428412","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I203339264","https://openalex.org/I203339264","https://openalex.org/I4210144566"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Alain Darte","raw_affiliation_strings":["LIP,UMR 5668 CNRS-ENS Lyon, UCB Lyon-Inria, France","LIP, UMR 5668 CNRS \u2014 ENS Lyon \u2014 UCB Lyon \u2014 Inria, France"],"affiliations":[{"raw_affiliation_string":"LIP,UMR 5668 CNRS-ENS Lyon, UCB Lyon-Inria, France","institution_ids":["https://openalex.org/I113428412","https://openalex.org/I100532134","https://openalex.org/I1294671590"]},{"raw_affiliation_string":"LIP, UMR 5668 CNRS \u2014 ENS Lyon \u2014 UCB Lyon \u2014 Inria, France","institution_ids":["https://openalex.org/I4210144566","https://openalex.org/I100532134","https://openalex.org/I1326498283","https://openalex.org/I1294671590","https://openalex.org/I113428412"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5086821977","display_name":"Alexandra Plesco","orcid":null},"institutions":[{"id":"https://openalex.org/I100532134","display_name":"Universit\u00e9 Claude Bernard Lyon 1","ror":"https://ror.org/029brtt94","country_code":"FR","type":"education","lineage":["https://openalex.org/I100532134","https://openalex.org/I203339264"]},{"id":"https://openalex.org/I113428412","display_name":"\u00c9cole Normale Sup\u00e9rieure de Lyon","ror":"https://ror.org/04zmssz18","country_code":"FR","type":"education","lineage":["https://openalex.org/I113428412","https://openalex.org/I203339264"]},{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I1326498283","display_name":"Institut national de recherche en sciences et technologies du num\u00e9rique","ror":"https://ror.org/02kvxyf05","country_code":"FR","type":"government","lineage":["https://openalex.org/I1326498283"]},{"id":"https://openalex.org/I4210144566","display_name":"Laboratoire de l'Informatique du Parall\u00e9lisme","ror":"https://ror.org/04msnz457","country_code":"FR","type":"facility","lineage":["https://openalex.org/I100532134","https://openalex.org/I113428412","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I203339264","https://openalex.org/I203339264","https://openalex.org/I4210144566"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Alexandra Plesco","raw_affiliation_strings":["LIP,UMR 5668 CNRS-ENS Lyon, UCB Lyon-Inria, France","LIP, UMR 5668 CNRS \u2014 ENS Lyon \u2014 UCB Lyon \u2014 Inria, France"],"affiliations":[{"raw_affiliation_string":"LIP,UMR 5668 CNRS-ENS Lyon, UCB Lyon-Inria, France","institution_ids":["https://openalex.org/I113428412","https://openalex.org/I100532134","https://openalex.org/I1294671590"]},{"raw_affiliation_string":"LIP, UMR 5668 CNRS \u2014 ENS Lyon \u2014 UCB Lyon \u2014 Inria, France","institution_ids":["https://openalex.org/I4210144566","https://openalex.org/I100532134","https://openalex.org/I1326498283","https://openalex.org/I1294671590","https://openalex.org/I113428412"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5010785753"],"corresponding_institution_ids":["https://openalex.org/I100532134","https://openalex.org/I113428412","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I4210144566"],"apc_list":null,"apc_paid":null,"fwci":1.5161,"has_fulltext":true,"cited_by_count":8,"citation_normalized_percentile":{"value":0.84299135,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"329","last_page":"332"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8237260580062866},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.6333991885185242},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.6315352916717529},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.6247025728225708},{"id":"https://openalex.org/keywords/interfacing","display_name":"Interfacing","score":0.5950573682785034},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5735846161842346},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5562364459037781},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4710017740726471},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.456502765417099},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.4336813986301422},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.43357133865356445},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.41483959555625916},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2683075964450836}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8237260580062866},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6333991885185242},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.6315352916717529},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.6247025728225708},{"id":"https://openalex.org/C2776303644","wikidata":"https://www.wikidata.org/wiki/Q1020499","display_name":"Interfacing","level":2,"score":0.5950573682785034},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5735846161842346},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5562364459037781},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4710017740726471},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.456502765417099},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.4336813986301422},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.43357133865356445},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.41483959555625916},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2683075964450836},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/asap.2010.5540967","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2010.5540967","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:inria-00482035v1","is_oa":true,"landing_page_url":"https://inria.hal.science/inria-00482035","pdf_url":"https://inria.hal.science/inria-00482035/document","source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"[Research Report] RR-7281, INRIA. 2010, pp.19","raw_type":"Reports"},{"id":"pmh:oai:HAL:hal-01664033v1","is_oa":true,"landing_page_url":"https://inria.hal.science/hal-01664033","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'10), Jul 2010, Rennes, France","raw_type":"Conference papers"}],"best_oa_location":{"id":"pmh:oai:HAL:inria-00482035v1","is_oa":true,"landing_page_url":"https://inria.hal.science/inria-00482035","pdf_url":"https://inria.hal.science/inria-00482035/document","source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"[Research Report] RR-7281, INRIA. 2010, pp.19","raw_type":"Reports"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/8","score":0.47999998927116394,"display_name":"Decent work and economic growth"}],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2132257274.pdf","grobid_xml":"https://content.openalex.org/works/W2132257274.grobid-xml"},"referenced_works_count":22,"referenced_works":["https://openalex.org/W37253703","https://openalex.org/W1503700136","https://openalex.org/W1533186609","https://openalex.org/W1604677972","https://openalex.org/W1975104688","https://openalex.org/W1976414351","https://openalex.org/W1994994277","https://openalex.org/W2034761517","https://openalex.org/W2038495591","https://openalex.org/W2073855204","https://openalex.org/W2077805988","https://openalex.org/W2102885578","https://openalex.org/W2111849853","https://openalex.org/W2120961842","https://openalex.org/W2128544270","https://openalex.org/W2165187428","https://openalex.org/W2326434185","https://openalex.org/W2482246557","https://openalex.org/W2802709660","https://openalex.org/W3145997180","https://openalex.org/W4285719527","https://openalex.org/W6701565172"],"related_works":["https://openalex.org/W2111408175","https://openalex.org/W1492116303","https://openalex.org/W1843355381","https://openalex.org/W1986121963","https://openalex.org/W2069295582","https://openalex.org/W2005854230","https://openalex.org/W2168113051","https://openalex.org/W90186386","https://openalex.org/W181593118","https://openalex.org/W2537479781"],"abstract_inverted_index":{"Thanks":[0],"to":[1,37,48,56,74,84,89,97,158],"efficient":[2,59],"scheduling,":[3],"resource":[4],"sharing,":[5],"and":[6,70,96],"finite-state":[7],"machines":[8],"generation,":[9],"high-level":[10,144],"synthesis":[11],"(HLS)":[12],"tools":[13,125,163],"are":[14],"now":[15],"more":[16],"mature":[17],"for":[18,132,140,160],"generating":[19],"hardware":[20],"accelerators":[21,72],"with":[22,34,101,110,143],"an":[23,58,75],"optimized":[24,35],"internal":[25],"structure.":[26],"But":[27],"interfacing":[28],"them":[29,99],"within":[30],"the":[31,39,51,62,66,86,105,114,138,156],"complete":[32],"design,":[33],"communications,":[36],"achieve":[38],"best":[40],"throughput":[41],"remains":[42],"hard.":[43],"Expert":[44],"designers":[45],"still":[46],"need":[47],"program":[49],"all":[50,100],"necessary":[52],"glue":[53],"(in":[54],"VHDL/Verilog)":[55],"get":[57],"design.":[60],"Taking":[61],"example":[63],"of":[64,71,113,149],"C2H,":[65,102],"Altera":[67],"HLS":[68,124,162],"tool,":[69],"communicating":[73],"external":[76],"DDR":[77],"memory,":[78],"we":[79],"show":[80],"it":[81,136],"is":[82,108,137,155],"possible":[83],"restructure":[85],"application":[87,107],"code,":[88],"generate":[90],"adequate":[91],"communication":[92],"processes,":[93],"in":[94],"C,":[95],"compile":[98],"so":[103],"that":[104,123],"resulting":[106],"highly-optimized,":[109],"full":[111],"usage":[112],"memory":[115],"bandwidth.":[116],"In":[117],"other":[118],"words,":[119],"our":[120],"study":[121],"demonstrates":[122],"can":[126],"be":[127],"used":[128],"as":[129,135],"back-end":[130],"optimizers":[131],"front-end":[133],"optimizations,":[134],"case":[139],"standard":[141],"compilation":[142],"transformations":[145],"developed":[146],"on":[147],"top":[148],"assembly-code":[150],"optimizers.":[151],"We":[152],"believe":[153],"this":[154],"way":[157],"go":[159],"making":[161],"viable.":[164]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":3}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
