{"id":"https://openalex.org/W7130578119","doi":"https://doi.org/10.1109/apccas67402.2025.11377061","title":"An IREE Compiler-Based SoC Design for Efficient on-Device AI Inference Acceleration","display_name":"An IREE Compiler-Based SoC Design for Efficient on-Device AI Inference Acceleration","publication_year":2025,"publication_date":"2025-10-12","ids":{"openalex":"https://openalex.org/W7130578119","doi":"https://doi.org/10.1109/apccas67402.2025.11377061"},"language":null,"primary_location":{"id":"doi:10.1109/apccas67402.2025.11377061","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas67402.2025.11377061","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5123053381","display_name":"Suhwan Park","orcid":null},"institutions":[{"id":"https://openalex.org/I191879574","display_name":"Inha University","ror":"https://ror.org/01easw929","country_code":"KR","type":"education","lineage":["https://openalex.org/I191879574"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Suhwan Park","raw_affiliation_strings":["Inha University,Department of Electrical and Computer Engineering,Incheon,South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Inha University,Department of Electrical and Computer Engineering,Incheon,South Korea","institution_ids":["https://openalex.org/I191879574"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5123031055","display_name":"Sangcheol Park","orcid":null},"institutions":[{"id":"https://openalex.org/I191879574","display_name":"Inha University","ror":"https://ror.org/01easw929","country_code":"KR","type":"education","lineage":["https://openalex.org/I191879574"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Sangcheol Park","raw_affiliation_strings":["Inha University,Department of Electrical and Computer Engineering,Incheon,South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Inha University,Department of Electrical and Computer Engineering,Incheon,South Korea","institution_ids":["https://openalex.org/I191879574"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111648922","display_name":"Jin Ku Kang","orcid":null},"institutions":[{"id":"https://openalex.org/I191879574","display_name":"Inha University","ror":"https://ror.org/01easw929","country_code":"KR","type":"education","lineage":["https://openalex.org/I191879574"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jin-Ku Kang","raw_affiliation_strings":["Inha University,Department of Electrical and Computer Engineering,Incheon,South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Inha University,Department of Electrical and Computer Engineering,Incheon,South Korea","institution_ids":["https://openalex.org/I191879574"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5123001321","display_name":"Yongwoo Kim","orcid":null},"institutions":[{"id":"https://openalex.org/I141074810","display_name":"Korea National University of Education","ror":"https://ror.org/03c9fpk55","country_code":"KR","type":"education","lineage":["https://openalex.org/I141074810"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Yongwoo Kim","raw_affiliation_strings":["Korea National University of Education,Department of Technology Education,Cheongju,South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Korea National University of Education,Department of Technology Education,Cheongju,South Korea","institution_ids":["https://openalex.org/I141074810"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.79935032,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T14347","display_name":"Big Data and Digital Economy","score":0.1331000030040741,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T14347","display_name":"Big Data and Digital Economy","score":0.1331000030040741,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.10419999808073044,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10036","display_name":"Advanced Neural Network Applications","score":0.0869000032544136,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/inference","display_name":"Inference","score":0.6352999806404114},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5156999826431274},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5002999901771545},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.45210000872612},{"id":"https://openalex.org/keywords/representation","display_name":"Representation (politics)","score":0.3725000023841858},{"id":"https://openalex.org/keywords/microblaze","display_name":"MicroBlaze","score":0.35929998755455017},{"id":"https://openalex.org/keywords/analyser","display_name":"Analyser","score":0.3334999978542328},{"id":"https://openalex.org/keywords/applications-of-artificial-intelligence","display_name":"Applications of artificial intelligence","score":0.32989999651908875},{"id":"https://openalex.org/keywords/inference-engine","display_name":"Inference engine","score":0.32760000228881836}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8032000064849854},{"id":"https://openalex.org/C2776214188","wikidata":"https://www.wikidata.org/wiki/Q408386","display_name":"Inference","level":2,"score":0.6352999806404114},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6234999895095825},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5156999826431274},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5002999901771545},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.45210000872612},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.38749998807907104},{"id":"https://openalex.org/C2776359362","wikidata":"https://www.wikidata.org/wiki/Q2145286","display_name":"Representation (politics)","level":3,"score":0.3725000023841858},{"id":"https://openalex.org/C2777575374","wikidata":"https://www.wikidata.org/wiki/Q1644704","display_name":"MicroBlaze","level":3,"score":0.35929998755455017},{"id":"https://openalex.org/C26834552","wikidata":"https://www.wikidata.org/wiki/Q3275846","display_name":"Analyser","level":2,"score":0.3334999978542328},{"id":"https://openalex.org/C157170001","wikidata":"https://www.wikidata.org/wiki/Q4781507","display_name":"Applications of artificial intelligence","level":2,"score":0.32989999651908875},{"id":"https://openalex.org/C46743427","wikidata":"https://www.wikidata.org/wiki/Q1341685","display_name":"Inference engine","level":3,"score":0.32760000228881836},{"id":"https://openalex.org/C2779818221","wikidata":"https://www.wikidata.org/wiki/Q837330","display_name":"Bytecode","level":3,"score":0.32249999046325684},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.3124000132083893},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.3070000112056732},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.3027999997138977},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.29280000925064087},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.289000004529953},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.2856999933719635},{"id":"https://openalex.org/C186967261","wikidata":"https://www.wikidata.org/wiki/Q5082128","display_name":"Mobile device","level":2,"score":0.271699994802475},{"id":"https://openalex.org/C47487241","wikidata":"https://www.wikidata.org/wiki/Q5227230","display_name":"Data access","level":2,"score":0.26409998536109924},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.262800008058548},{"id":"https://openalex.org/C162307627","wikidata":"https://www.wikidata.org/wiki/Q204833","display_name":"Enhanced Data Rates for GSM Evolution","level":2,"score":0.2603999972343445},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.259799987077713},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.2581000030040741},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.25369998812675476},{"id":"https://openalex.org/C98025372","wikidata":"https://www.wikidata.org/wiki/Q477538","display_name":"Systems architecture","level":3,"score":0.2513999938964844},{"id":"https://openalex.org/C117896860","wikidata":"https://www.wikidata.org/wiki/Q11376","display_name":"Acceleration","level":2,"score":0.25040000677108765},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.2500999867916107}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas67402.2025.11377061","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas67402.2025.11377061","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G5673596265","display_name":null,"funder_award_id":"RS-2021-11212052","funder_id":"https://openalex.org/F4320328359","funder_display_name":"Ministry of Science and ICT, South Korea"}],"funders":[{"id":"https://openalex.org/F4320328359","display_name":"Ministry of Science and ICT, South Korea","ror":"https://ror.org/01wpjm123"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W3205567719","https://openalex.org/W4388230802","https://openalex.org/W4403865930","https://openalex.org/W4409796198"],"related_works":[],"abstract_inverted_index":{"As":[0],"on-device":[1],"inference":[2,115,130],"gains":[3],"traction":[4],"for":[5,17,132,139],"privacy":[6],"protection":[7],"and":[8,19,61,69,79,88,105,107],"low-latency":[9],"AI":[10,134],"services":[11],"in":[12,114],"edge":[13],"environments,":[14],"the":[15,119,125,137],"demand":[16],"flexible":[18],"lightweight":[20],"SoC":[21,30],"architecture":[22],"is":[23,53],"increasing.":[24],"This":[25,122],"paper":[26],"proposes":[27],"a":[28,48,56,64],"novel":[29],"design":[31],"that":[32],"directly":[33],"executes":[34,97],"IREE":[35],"(Intermediate":[36],"Representation":[37],"Execution":[38],"Environment)":[39],"VM":[40],"Bytecode":[41],"through":[42],"an":[43,70],"interpreter-based":[44],"approach":[45],"implemented":[46],"on":[47,55,118],"RISC-V":[49],"core.":[50],"The":[51,93],"system":[52,95],"validated":[54],"Zynq":[57],"ZC706":[58],"FPGA":[59],"board":[60],"consists":[62],"of":[63,127],"compiler-hosted":[65],"PS":[66],"(Processing":[67],"System)":[68],"interpreterexecuting":[71],"PL":[72],"(Programmable":[73],"Logic).":[74],"To":[75],"improve":[76],"performance,":[77],"DMA":[78],"cache":[80],"modules":[81],"are":[82],"integrated":[83],"to":[84,110],"optimize":[85],"data":[86],"movement":[87],"memory":[89],"access":[90],"during":[91],"inference.":[92],"proposed":[94],"successfully":[96],"various":[98],"machine":[99],"learning":[100],"models,":[101],"including":[102],"MUL,":[103],"MMT,":[104],"MNIST,":[106],"achieves":[108],"up":[109],"29":[111],"%":[112],"reduction":[113],"time":[116],"depending":[117],"model":[120],"characteristics.":[121],"work":[123],"demonstrates":[124],"feasibility":[126],"compiler-driven,":[128],"reconfigurable":[129],"architectures":[131],"embedded":[133],"applications":[135],"without":[136],"need":[138],"model-specific":[140],"hardware":[141],"redesign.":[142]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2026-02-20T00:00:00"}