{"id":"https://openalex.org/W2148714817","doi":"https://doi.org/10.1109/apccas.2012.6418963","title":"A robust NTF zero optimization technique for both low and high OSRs sigma-delta modulators","display_name":"A robust NTF zero optimization technique for both low and high OSRs sigma-delta modulators","publication_year":2012,"publication_date":"2012-12-01","ids":{"openalex":"https://openalex.org/W2148714817","doi":"https://doi.org/10.1109/apccas.2012.6418963","mag":"2148714817"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2012.6418963","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2012.6418963","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE Asia Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109071954","display_name":"Yun Du","orcid":"https://orcid.org/0009-0005-6117-1780"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Yun Du","raw_affiliation_strings":["State-Key Laboratory of Analog and Mixed Signal VLSI, Faculty of Science and Technology, University of Macau, Macao, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State-Key Laboratory of Analog and Mixed Signal VLSI, Faculty of Science and Technology, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101688425","display_name":"Tao He","orcid":"https://orcid.org/0000-0002-9351-7329"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Tao He","raw_affiliation_strings":["State-Key Laboratory of Analog and Mixed Signal VLSI, Faculty of Science and Technology, University of Macau, Macao, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State-Key Laboratory of Analog and Mixed Signal VLSI, Faculty of Science and Technology, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003985219","display_name":"Yang Jiang","orcid":"https://orcid.org/0000-0003-2577-4259"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Yang Jiang","raw_affiliation_strings":["State-Key Laboratory of Analog and Mixed Signal VLSI, Faculty of Science and Technology, University of Macau, Macao, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State-Key Laboratory of Analog and Mixed Signal VLSI, Faculty of Science and Technology, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073702117","display_name":"Sai\u2010Weng Sin","orcid":"https://orcid.org/0000-0001-9346-8291"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Sai-Weng Sin","raw_affiliation_strings":["State-Key Laboratory of Analog and Mixed Signal VLSI, Faculty of Science and Technology, University of Macau, Macao, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State-Key Laboratory of Analog and Mixed Signal VLSI, Faculty of Science and Technology, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061042931","display_name":"U Seng\u2010Pan","orcid":null},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Seng-Pan U","raw_affiliation_strings":["State-Key Laboratory of Analog and Mixed Signal VLSI, Faculty of Science and Technology, University of Macau, Macao, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State-Key Laboratory of Analog and Mixed Signal VLSI, Faculty of Science and Technology, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5106943352","display_name":"Rui P. Martins","orcid":"https://orcid.org/0000-0003-2821-648X"},"institutions":[{"id":"https://openalex.org/I203847022","display_name":"Instituto Polit\u00e9cnico de Lisboa","ror":"https://ror.org/04ea70f07","country_code":"PT","type":"education","lineage":["https://openalex.org/I203847022"]},{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO","PT"],"is_corresponding":false,"raw_author_name":"R.P. Martins","raw_affiliation_strings":["Instituto Superior T\u00e9cnico, Technical University of Lisbon, Portugal","State-Key Laboratory of Analog and Mixed Signal VLSI, Faculty of Science and Technology, University of Macau, Macao, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto Superior T\u00e9cnico, Technical University of Lisbon, Portugal","institution_ids":["https://openalex.org/I203847022"]},{"raw_affiliation_string":"State-Key Laboratory of Analog and Mixed Signal VLSI, Faculty of Science and Technology, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2071,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.59417769,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"29","last_page":"32"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/oversampling","display_name":"Oversampling","score":0.8646045923233032},{"id":"https://openalex.org/keywords/delta-sigma-modulation","display_name":"Delta-sigma modulation","score":0.7655560970306396},{"id":"https://openalex.org/keywords/transfer-function","display_name":"Transfer function","score":0.6382749080657959},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.5729995369911194},{"id":"https://openalex.org/keywords/sensitivity","display_name":"Sensitivity (control systems)","score":0.5382241010665894},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.5262086987495422},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.48965054750442505},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.4634639322757721},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.4624725878238678},{"id":"https://openalex.org/keywords/feedback-loop","display_name":"Feedback loop","score":0.42529892921447754},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4250982403755188},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19870370626449585},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08999171853065491},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08303722739219666}],"concepts":[{"id":"https://openalex.org/C197323446","wikidata":"https://www.wikidata.org/wiki/Q331222","display_name":"Oversampling","level":3,"score":0.8646045923233032},{"id":"https://openalex.org/C68754193","wikidata":"https://www.wikidata.org/wiki/Q1184820","display_name":"Delta-sigma modulation","level":3,"score":0.7655560970306396},{"id":"https://openalex.org/C81299745","wikidata":"https://www.wikidata.org/wiki/Q334269","display_name":"Transfer function","level":2,"score":0.6382749080657959},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.5729995369911194},{"id":"https://openalex.org/C21200559","wikidata":"https://www.wikidata.org/wiki/Q7451068","display_name":"Sensitivity (control systems)","level":2,"score":0.5382241010665894},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.5262086987495422},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.48965054750442505},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.4634639322757721},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.4624725878238678},{"id":"https://openalex.org/C186886427","wikidata":"https://www.wikidata.org/wiki/Q5441213","display_name":"Feedback loop","level":2,"score":0.42529892921447754},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4250982403755188},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19870370626449585},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08999171853065491},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08303722739219666},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2012.6418963","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2012.6418963","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE Asia Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.6800000071525574}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W118952169","https://openalex.org/W605564925","https://openalex.org/W1519269051","https://openalex.org/W1531446014","https://openalex.org/W2073140918","https://openalex.org/W2088625373","https://openalex.org/W2099740767","https://openalex.org/W2135193059","https://openalex.org/W4285719527","https://openalex.org/W4301627548"],"related_works":["https://openalex.org/W2040229502","https://openalex.org/W1580014081","https://openalex.org/W2421111280","https://openalex.org/W2097165798","https://openalex.org/W1497881430","https://openalex.org/W2599174517","https://openalex.org/W2117483815","https://openalex.org/W2170102475","https://openalex.org/W3175904419","https://openalex.org/W2545192519"],"abstract_inverted_index":{"This":[0,20],"paper":[1],"introduces":[2],"a":[3,17,97],"novel":[4],"loop":[5,52,77],"filter":[6,78],"scheme":[7],"with":[8,42,49,74,83,100],"embedded":[9],"noise":[10],"transfer":[11],"function":[12],"(NTF)":[13],"zero":[14,38],"optimization":[15,39],"in":[16,96,107],"feed-forward":[18],"topology.":[19],"new":[21],"structure":[22],"allows":[23],"the":[24,27,30,35,50,55,62,75,90,104,108],"relaxation":[25],"of":[26,29,37,89],"requirement":[28],"local":[31,109],"feedback":[32,110],"coefficient.":[33],"Moreover,":[34],"merit":[36],"is":[40,79],"compatible":[41],"high":[43],"oversampling":[44],"ratio":[45,64],"(OSR)":[46],"when":[47],"compared":[48],"traditional":[51],"filter.":[53],"Besides,":[54],"practical":[56],"implementation":[57],"exhibits":[58],"less":[59],"sensitivity":[60],"to":[61],"capacitor":[63],"mismatches.":[65],"A":[66],"second":[67],"order":[68],"discrete-time":[69],"(DT)":[70],"sigma-delta":[71],"(\u03a3\u0394)":[72],"modulator":[73,91],"proposed":[76],"designed":[80],"and":[81,85,103],"simulated":[82],"Matlab":[84],"Cadence.":[86],"The":[87],"performance":[88],"can":[92],"reach":[93],"70.1dB/99.3dB":[94],"SNDR":[95],"10MHz":[98],"bandwidth,":[99],"OSR":[101],"12/48":[102],"corresponding":[105],"coefficients":[106],"0.4/0.34,":[111],"respectively.":[112]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}