{"id":"https://openalex.org/W2033179656","doi":"https://doi.org/10.1109/54.953276","title":"Online and offline BIST in IP-core design","display_name":"Online and offline BIST in IP-core design","publication_year":2001,"publication_date":"2001-01-01","ids":{"openalex":"https://openalex.org/W2033179656","doi":"https://doi.org/10.1109/54.953276","mag":"2033179656"},"language":"en","primary_location":{"id":"doi:10.1109/54.953276","is_oa":false,"landing_page_url":"https://doi.org/10.1109/54.953276","pdf_url":null,"source":{"id":"https://openalex.org/S73404582","display_name":"IEEE Design & Test of Computers","issn_l":"0740-7475","issn":["0740-7475","1558-1918"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design & Test of Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://porto.polito.it/1398122/","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030177680","display_name":"Alfredo Benso","orcid":"https://orcid.org/0000-0003-3433-7739"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"A. Benso","raw_affiliation_strings":["Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino TO, Italy","Politecnico di Torino, Torino, Piemonte, IT"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino TO, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Politecnico di Torino, Torino, Piemonte, IT","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076491770","display_name":"S. Chinsano","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"S. Chinsano","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078888989","display_name":"Giorgio Di Natale","orcid":"https://orcid.org/0000-0001-8063-5388"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"G. Di Natale","raw_affiliation_strings":["Dipartimento di Automatica e Informatica, Politecnico di Torino, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036258272","display_name":"P. Prinetto","orcid":"https://orcid.org/0000-0003-2400-8245"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"P. Prinetto","raw_affiliation_strings":["Dipartimento di Automatica e Informatica, Politecnico di Torino, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011504311","display_name":"M.L. Bodoni","orcid":null},"institutions":[{"id":"https://openalex.org/I1325886976","display_name":"Siemens (Germany)","ror":"https://ror.org/059mq0909","country_code":"DE","type":"company","lineage":["https://openalex.org/I1325886976"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"M.L. Bodoni","raw_affiliation_strings":["Siemens Information and Communication Networks"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Siemens Information and Communication Networks","institution_ids":["https://openalex.org/I1325886976"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.5492,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.70544218,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"18","issue":"5","first_page":"92","last_page":"99"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6583033800125122},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.6233307719230652},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5778136253356934},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.5472584962844849},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5099347829818726},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.48169976472854614},{"id":"https://openalex.org/keywords/core","display_name":"Core (optical fiber)","score":0.4540201425552368},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.44959959387779236},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.43934914469718933},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3242640495300293},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.17441782355308533},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.15676307678222656},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0967378318309784}],"concepts":[{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6583033800125122},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.6233307719230652},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5778136253356934},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.5472584962844849},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5099347829818726},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.48169976472854614},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.4540201425552368},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.44959959387779236},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.43934914469718933},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3242640495300293},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.17441782355308533},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.15676307678222656},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0967378318309784},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/54.953276","is_oa":false,"landing_page_url":"https://doi.org/10.1109/54.953276","pdf_url":null,"source":{"id":"https://openalex.org/S73404582","display_name":"IEEE Design & Test of Computers","issn_l":"0740-7475","issn":["0740-7475","1558-1918"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design & Test of Computers","raw_type":"journal-article"},{"id":"pmh:oai:porto.polito.it:1398122","is_oa":true,"landing_page_url":"http://porto.polito.it/1398122/","pdf_url":null,"source":{"id":"https://openalex.org/S4306402038","display_name":"PORTO Publications Open Repository TOrino (Politecnico di Torino)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I177477856","host_organization_name":"Politecnico di Torino","host_organization_lineage":["https://openalex.org/I177477856"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ISSN:0740-7475","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"pmh:oai:porto.polito.it:1398122","is_oa":true,"landing_page_url":"http://porto.polito.it/1398122/","pdf_url":null,"source":{"id":"https://openalex.org/S4306402038","display_name":"PORTO Publications Open Repository TOrino (Politecnico di Torino)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I177477856","host_organization_name":"Politecnico di Torino","host_organization_lineage":["https://openalex.org/I177477856"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ISSN:0740-7475","raw_type":"info:eu-repo/semantics/article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.4699999988079071}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W289624287","https://openalex.org/W1548975601","https://openalex.org/W1606480398","https://openalex.org/W1906369229","https://openalex.org/W1957909232","https://openalex.org/W2028504835","https://openalex.org/W2096229678","https://openalex.org/W2106935654","https://openalex.org/W2115521620","https://openalex.org/W2121938580","https://openalex.org/W2139254411","https://openalex.org/W4206707433","https://openalex.org/W4247767635"],"related_works":["https://openalex.org/W3151633427","https://openalex.org/W2012045996","https://openalex.org/W2212894501","https://openalex.org/W2793465010","https://openalex.org/W3024050170","https://openalex.org/W4293253840","https://openalex.org/W4378977321","https://openalex.org/W2967161359","https://openalex.org/W4308090481","https://openalex.org/W91363257"],"abstract_inverted_index":{"This":[0],"article":[1],"presents":[2],"an":[3,12],"online":[4],"and":[5,27],"offline":[6],"built-in":[7],"self-test":[8],"architecture":[9,20],"implemented":[10],"as":[11],"SRAM":[13],"intellectual-property":[14],"core":[15],"for":[16],"telecommunication":[17],"applications.":[18],"The":[19],"combines":[21],"fault-latency":[22],"reduction,":[23],"code-based":[24],"fault":[25,29],"detection,":[26],"architecture-based":[28],"avoidance":[30],"to":[31],"meet":[32],"reliability":[33],"constraints.":[34]},"counts_by_year":[{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}