{"id":"https://openalex.org/W2150786077","doi":"https://doi.org/10.1109/54.655184","title":"Integrating online and offline testing of a switching memory","display_name":"Integrating online and offline testing of a switching memory","publication_year":1998,"publication_date":"1998-01-01","ids":{"openalex":"https://openalex.org/W2150786077","doi":"https://doi.org/10.1109/54.655184","mag":"2150786077"},"language":"en","primary_location":{"id":"doi:10.1109/54.655184","is_oa":false,"landing_page_url":"https://doi.org/10.1109/54.655184","pdf_url":null,"source":{"id":"https://openalex.org/S73404582","display_name":"IEEE Design & Test of Computers","issn_l":"0740-7475","issn":["0740-7475","1558-1918"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test of Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5045235975","display_name":"S. Barbagallo","orcid":"https://orcid.org/0000-0001-7488-0037"},"institutions":[{"id":"https://openalex.org/I2799464224","display_name":"Italtel (Italy)","ror":"https://ror.org/012ae7p27","country_code":"IT","type":"company","lineage":["https://openalex.org/I2799464224"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"S. Barbagallo","raw_affiliation_strings":["Italtel, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Italtel, Italy","institution_ids":["https://openalex.org/I2799464224"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112603308","display_name":"D. Medina","orcid":null},"institutions":[{"id":"https://openalex.org/I2799464224","display_name":"Italtel (Italy)","ror":"https://ror.org/012ae7p27","country_code":"IT","type":"company","lineage":["https://openalex.org/I2799464224"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"D. Medina","raw_affiliation_strings":["Italtel, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Italtel, Italy","institution_ids":["https://openalex.org/I2799464224"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060510787","display_name":"Fulvio Corno","orcid":"https://orcid.org/0000-0002-9818-0999"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"F. Corno","raw_affiliation_strings":["Politecnico di Turino, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Politecnico di Turino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036258272","display_name":"P. Prinetto","orcid":"https://orcid.org/0000-0003-2400-8245"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"P. Prinetto","raw_affiliation_strings":["Politecnico di Turino, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Politecnico di Turino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5058555274","display_name":"M. Sonza Reorda","orcid":"https://orcid.org/0000-0003-2899-7669"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M.S. Reorda","raw_affiliation_strings":["Politecnico di Turino, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Politecnico di Turino, Italy","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.7259,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.74838228,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":"15","issue":"1","first_page":"63","last_page":"70"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.988099992275238,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/boundary-scan","display_name":"Boundary scan","score":0.8390061855316162},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6519293785095215},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5552418828010559},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.4636911153793335},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.44058138132095337},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.43770989775657654},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.42888548970222473},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.405588299036026},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.359561562538147},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.26721465587615967},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.26371437311172485},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2340296506881714},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.18208056688308716},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.17716571688652039},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.1213834285736084},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11370149254798889},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.09924986958503723}],"concepts":[{"id":"https://openalex.org/C992767","wikidata":"https://www.wikidata.org/wiki/Q895156","display_name":"Boundary scan","level":3,"score":0.8390061855316162},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6519293785095215},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5552418828010559},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.4636911153793335},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.44058138132095337},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.43770989775657654},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.42888548970222473},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.405588299036026},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.359561562538147},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.26721465587615967},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.26371437311172485},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2340296506881714},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.18208056688308716},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.17716571688652039},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.1213834285736084},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11370149254798889},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.09924986958503723},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/54.655184","is_oa":false,"landing_page_url":"https://doi.org/10.1109/54.655184","pdf_url":null,"source":{"id":"https://openalex.org/S73404582","display_name":"IEEE Design & Test of Computers","issn_l":"0740-7475","issn":["0740-7475","1558-1918"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test of Computers","raw_type":"journal-article"},{"id":"pmh:oai:porto.polito.it:1404458","is_oa":false,"landing_page_url":"http://porto.polito.it/1404458/","pdf_url":null,"source":{"id":"https://openalex.org/S4306402038","display_name":"PORTO Publications Open Repository TOrino (Politecnico di Torino)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I177477856","host_organization_name":"Politecnico di Torino","host_organization_lineage":["https://openalex.org/I177477856"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ISSN:0740-7475","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1772932304","https://openalex.org/W2031337541","https://openalex.org/W2078286038","https://openalex.org/W2106935654","https://openalex.org/W2147675953","https://openalex.org/W2153199442","https://openalex.org/W4229543366"],"related_works":["https://openalex.org/W1852363244","https://openalex.org/W2166065438","https://openalex.org/W2145319894","https://openalex.org/W2168601023","https://openalex.org/W1975458101","https://openalex.org/W2127184179","https://openalex.org/W2380857293","https://openalex.org/W2137651210","https://openalex.org/W2550015578","https://openalex.org/W1969425693"],"abstract_inverted_index":{"A":[0],"circuit":[1],"used":[2],"in":[3],"a":[4],"telephone":[5],"switching":[6],"unit":[7],"features":[8],"several":[9],"test":[10],"techniques,":[11],"including":[12],"BIST,":[13],"partial":[14],"scan,":[15],"and":[16,27],"boundary":[17],"scan.":[18],"By":[19],"sharing":[20],"the":[21,30],"same":[22],"circuitry":[23],"for":[24],"both":[25],"online":[26],"offline":[28],"testing,":[29],"design":[31],"minimizes":[32],"additional":[33],"logic":[34],"while":[35],"achieving":[36],"very":[37],"high":[38],"fault":[39],"coverage.":[40]},"counts_by_year":[{"year":2014,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
