{"id":"https://openalex.org/W2131162223","doi":"https://doi.org/10.1109/4.509857","title":"On-Chip I/sub DDQ/ testability schemes for detecting multiple faults in CMOS ICs","display_name":"On-Chip I/sub DDQ/ testability schemes for detecting multiple faults in CMOS ICs","publication_year":1996,"publication_date":"1996-05-01","ids":{"openalex":"https://openalex.org/W2131162223","doi":"https://doi.org/10.1109/4.509857","mag":"2131162223"},"language":"en","primary_location":{"id":"doi:10.1109/4.509857","is_oa":false,"landing_page_url":"https://doi.org/10.1109/4.509857","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109227987","display_name":"Changku Hwang","orcid":null},"institutions":[{"id":"https://openalex.org/I52357470","display_name":"The Ohio State University","ror":"https://ror.org/00rs6vg23","country_code":"US","type":"education","lineage":["https://openalex.org/I52357470"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Changku Hwang","raw_affiliation_strings":["Department of Electrical Engineering, Ohio State Uinversity, Columbus, OH, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Ohio State Uinversity, Columbus, OH, USA","institution_ids":["https://openalex.org/I52357470"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101541085","display_name":"M. Ismail","orcid":"https://orcid.org/0000-0002-1997-6826"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"M. Ismail","raw_affiliation_strings":["Helsinki University of Technology, Espoo, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Helsinki University of Technology, Espoo, Finland","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5064024985","display_name":"Joanne DeGroat","orcid":null},"institutions":[{"id":"https://openalex.org/I52357470","display_name":"The Ohio State University","ror":"https://ror.org/00rs6vg23","country_code":"US","type":"education","lineage":["https://openalex.org/I52357470"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J.E. DeGroat","raw_affiliation_strings":["Department of Electrical Engineering, Ohio State Uinversity, Columbus, OH, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Ohio State Uinversity, Columbus, OH, USA","institution_ids":["https://openalex.org/I52357470"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3878,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.69469929,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"31","issue":"5","first_page":"732","last_page":"739"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.7145060896873474},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.7066789269447327},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6780016422271729},{"id":"https://openalex.org/keywords/subtractor","display_name":"Subtractor","score":0.6352023482322693},{"id":"https://openalex.org/keywords/arithmetic-logic-unit","display_name":"Arithmetic logic unit","score":0.6222683787345886},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5826960206031799},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.5296837091445923},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5230240225791931},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4732647240161896},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.43535780906677246},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.40002700686454773},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.36089766025543213},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3059263229370117},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25999167561531067},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.16960278153419495},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.12012317776679993},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.10287532210350037},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.060982346534729004}],"concepts":[{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.7145060896873474},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.7066789269447327},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6780016422271729},{"id":"https://openalex.org/C187805909","wikidata":"https://www.wikidata.org/wiki/Q1142401","display_name":"Subtractor","level":4,"score":0.6352023482322693},{"id":"https://openalex.org/C100276221","wikidata":"https://www.wikidata.org/wiki/Q192903","display_name":"Arithmetic logic unit","level":2,"score":0.6222683787345886},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5826960206031799},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.5296837091445923},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5230240225791931},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4732647240161896},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.43535780906677246},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.40002700686454773},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.36089766025543213},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3059263229370117},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25999167561531067},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.16960278153419495},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.12012317776679993},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.10287532210350037},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.060982346534729004},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/4.509857","is_oa":false,"landing_page_url":"https://doi.org/10.1109/4.509857","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1501285939","https://openalex.org/W1555253106","https://openalex.org/W1983496191","https://openalex.org/W2041406712","https://openalex.org/W2105872644","https://openalex.org/W2110771569","https://openalex.org/W2113116320","https://openalex.org/W2115729533","https://openalex.org/W2157748808","https://openalex.org/W2165186270","https://openalex.org/W2522991329","https://openalex.org/W4251013638","https://openalex.org/W4302985053"],"related_works":["https://openalex.org/W2959321197","https://openalex.org/W2157191248","https://openalex.org/W2107525390","https://openalex.org/W4206835326","https://openalex.org/W2782079150","https://openalex.org/W2164493372","https://openalex.org/W2153086993","https://openalex.org/W2114980936","https://openalex.org/W2118697956","https://openalex.org/W2128920253"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"we":[3],"present":[4],"two":[5,46],"on-chip":[6],"design-for-testability":[7],"(DFT)":[8],"schemes":[9,25],"for":[10,15,21,39],"CMOS":[11],"ICs.":[12],"One":[13],"is":[14,71],"small":[16,36],"circuits":[17],"and":[18,43],"the":[19,40,63,68],"other":[20],"large":[22],"circuits.":[23],"Both":[24],"identify":[26],"a":[27,31,35,74,84],"faulty":[28],"area":[29,37],"on":[30],"chip":[32],"with":[33,62],"only":[34],"overhead":[38],"additional":[41],"circuitry":[42],"at":[44],"most":[45],"extra":[47],"pins.":[48],"Moreover,":[49],"if":[50],"faults":[51,57],"occur":[52],"in":[53,73],"different":[54],"areas,":[55],"multiple":[56],"can":[58],"also":[59],"be":[60],"detected":[61],"proposed":[64],"schemes.":[65],"To":[66],"demonstrate":[67],"ideas,":[69],"DFT":[70],"incorporated":[72],"4-bit":[75],"carry":[76],"look":[77],"ahead":[78],"adder/subtractor":[79],"(CLAAS)":[80],"as":[81,83],"well":[82],"16-bit":[85],"arithmetic":[86],"logic":[87],"unit":[88],"(ALU).":[89],"Simulation":[90],"results":[91],"are":[92],"given.":[93]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
