{"id":"https://openalex.org/W2070960830","doi":"https://doi.org/10.1109/3dic.2013.6702397","title":"Design of controller for L2 cache mapped in Tezzaron stacked DRAM","display_name":"Design of controller for L2 cache mapped in Tezzaron stacked DRAM","publication_year":2013,"publication_date":"2013-10-01","ids":{"openalex":"https://openalex.org/W2070960830","doi":"https://doi.org/10.1109/3dic.2013.6702397","mag":"2070960830"},"language":"en","primary_location":{"id":"doi:10.1109/3dic.2013.6702397","is_oa":false,"landing_page_url":"https://doi.org/10.1109/3dic.2013.6702397","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International 3D Systems Integration Conference (3DIC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078773180","display_name":"Nyunyi Marcus Tshibangu","orcid":null},"institutions":[{"id":"https://openalex.org/I137902535","display_name":"North Carolina State University","ror":"https://ror.org/04tj63d06","country_code":"US","type":"education","lineage":["https://openalex.org/I137902535"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Nyunyi M. Tshibangu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, North Carolina State University Raleigh, NC, USA","Dept. of Electr. & Comput. Eng, North Carolina State Univ., Raleigh, NC, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, North Carolina State University Raleigh, NC, USA","institution_ids":["https://openalex.org/I137902535"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng, North Carolina State Univ., Raleigh, NC, USA","institution_ids":["https://openalex.org/I137902535"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074605796","display_name":"Paul D. Franzon","orcid":"https://orcid.org/0000-0002-6048-5770"},"institutions":[{"id":"https://openalex.org/I137902535","display_name":"North Carolina State University","ror":"https://ror.org/04tj63d06","country_code":"US","type":"education","lineage":["https://openalex.org/I137902535"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Paul D. Franzon","raw_affiliation_strings":["Department of Electrical and Computer Engineering, North Carolina State University Raleigh, NC, USA","Dept. of Electr. & Comput. Eng, North Carolina State Univ., Raleigh, NC, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, North Carolina State University Raleigh, NC, USA","institution_ids":["https://openalex.org/I137902535"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng, North Carolina State Univ., Raleigh, NC, USA","institution_ids":["https://openalex.org/I137902535"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090803057","display_name":"Eric Rotenberg","orcid":"https://orcid.org/0000-0002-0406-1973"},"institutions":[{"id":"https://openalex.org/I137902535","display_name":"North Carolina State University","ror":"https://ror.org/04tj63d06","country_code":"US","type":"education","lineage":["https://openalex.org/I137902535"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Eric Rotenberg","raw_affiliation_strings":["Department of Electrical and Computer Engineering, North Carolina State University Raleigh, NC, USA","Dept. of Electr. & Comput. Eng, North Carolina State Univ., Raleigh, NC, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, North Carolina State University Raleigh, NC, USA","institution_ids":["https://openalex.org/I137902535"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng, North Carolina State Univ., Raleigh, NC, USA","institution_ids":["https://openalex.org/I137902535"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000597593","display_name":"W. Rhett Davis","orcid":"https://orcid.org/0000-0002-9338-1441"},"institutions":[{"id":"https://openalex.org/I137902535","display_name":"North Carolina State University","ror":"https://ror.org/04tj63d06","country_code":"US","type":"education","lineage":["https://openalex.org/I137902535"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"William R. Davis","raw_affiliation_strings":["Department of Electrical and Computer Engineering, North Carolina State University Raleigh, NC, USA","Dept. of Electr. & Comput. Eng, North Carolina State Univ., Raleigh, NC, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, North Carolina State University Raleigh, NC, USA","institution_ids":["https://openalex.org/I137902535"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng, North Carolina State Univ., Raleigh, NC, USA","institution_ids":["https://openalex.org/I137902535"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5078773180"],"corresponding_institution_ids":["https://openalex.org/I137902535"],"apc_list":null,"apc_paid":null,"fwci":0.84235547,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.77892422,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8429787158966064},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7854700088500977},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.6142387986183167},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.5851861238479614},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.5726354718208313},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5409456491470337},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.47982025146484375},{"id":"https://openalex.org/keywords/page-cache","display_name":"Page cache","score":0.4590245187282562},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4457198977470398},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.41197535395622253},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.41192498803138733},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.40787041187286377},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.3383808732032776},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.21628332138061523}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8429787158966064},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7854700088500977},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.6142387986183167},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.5851861238479614},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.5726354718208313},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5409456491470337},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.47982025146484375},{"id":"https://openalex.org/C36340418","wikidata":"https://www.wikidata.org/wiki/Q7124288","display_name":"Page cache","level":5,"score":0.4590245187282562},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4457198977470398},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.41197535395622253},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41192498803138733},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.40787041187286377},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.3383808732032776},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.21628332138061523}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/3dic.2013.6702397","is_oa":false,"landing_page_url":"https://doi.org/10.1109/3dic.2013.6702397","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International 3D Systems Integration Conference (3DIC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.9100000262260437,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2023264348","https://openalex.org/W2147657366","https://openalex.org/W2148797773"],"related_works":["https://openalex.org/W2082939521","https://openalex.org/W2547220881","https://openalex.org/W2020176098","https://openalex.org/W2012518269","https://openalex.org/W2363672756","https://openalex.org/W1496086148","https://openalex.org/W2086718556","https://openalex.org/W2077899426","https://openalex.org/W1860107648","https://openalex.org/W1965891727"],"abstract_inverted_index":{"3DIC":[0],"technology":[1],"allows":[2],"implementation":[3,53],"of":[4,13,31,41,54,92,101,137,144,182],"fast":[5,34,71],"and":[6,43,76,155],"dense":[7],"memory":[8,68],"by":[9,38],"allowing":[10],"multiple":[11,81],"layers":[12],"DRAM":[14,32],"to":[15,28,168,173],"be":[16,104],"fabricated":[17],"in":[18,45,89,106,164],"a":[19,56,70,95,128,140,174],"single":[20],"die":[21],"called":[22],"Die-stacking":[23],"technology.":[24],"This":[25,49,67,150,159],"creates":[26],"opportunity":[27],"explore":[29],"usage":[30],"as":[33],"last":[35],"level":[36],"cache":[37,57,97,114],"exploiting":[39],"mapping":[40],"data":[42,72,102,126],"tag":[44,119],"the":[46,52,84,135,170],"same":[47],"bank.":[48],"Paper":[50],"investigates":[51],"such":[55],"controller":[58],"using":[59],"3-layer":[60],"256":[61],"MB":[62],"Tezzaron":[63,138],"Octopus":[64],"stacked":[65],"DRAM.":[66],"provides":[69],"access":[73,160],"through":[74],"burst-4":[75],"burst-8":[77],"mode.":[78],"To":[79],"avoid":[80],"row":[82,91,156],"activation,":[83],"entire":[85],"set":[86,130],"is":[87,186],"confined":[88],"one":[90,107],"2KB.":[93],"For":[94],"64B":[96],"block,":[98],"32":[99],"lines":[100],"can":[103],"obtained":[105],"row.":[108],"In":[109],"this":[110],"design,":[111],"only":[112],"two":[113],"blocks":[115,122],"are":[116,123],"used":[117,124,163],"for":[118,125],"while":[120,191],"30":[121],"yielding":[127],"30-way":[129],"associative":[131],"L2":[132,178],"cache.":[133,179],"Given":[134],"performance":[136,171,185],"memory,":[139],"low":[141],"hit":[142,151],"time":[143],"approximately":[145],"20":[146],"cycles":[147],"was":[148,162],"achieved.":[149],"latency":[152,161],"includes":[153],"precharge":[154],"activation":[157],"delays.":[158],"Gem5":[165],"full-system":[166],"simulator":[167],"estimate":[169],"compared":[172],"standard":[175],"2D":[176],"SRAM":[177],"An":[180],"average":[181,194],"15%":[183],"on":[184,188,196],"achieved":[187],"different":[189],"benchmarks":[190],"providing":[192],"an":[193],"27%":[195],"energy":[197],"saving.":[198]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
